View AD9925_354552.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CCD Signal Processor with Vertical Driver and Precision Timing TM Generator AD9925
FEATURES
Integrated 10-channel V-driver Register-compatible with the AD9991 and AD9995 3-field (6-phase) vertical clock support 2 additional vertical outputs for advanced CCDs Complete on-chip timing generator Precision Timing core with <600 ps resolution Correlated double sampler (CDS) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-bit 36 MHz ADC Black level clamp with variable level control On-chip 3 V horizontal and RG drivers 2-phase and 4-phase H-clock modes Electronic and mechanical shutter support On-chip driver for external crystal On-chip sync generator with external sync input 8 mm x 8 mm CSPBGA package with 0.65 mm pitch
GENERAL DESCRIPTION
The AD9925 is a complete 36 MHz front end solution for digital still camera and other CCD imaging applications. Based on the AD9995 product, the AD9925 includes the analog front end and a fully programmable timing generator (AFETG), combined with a 10-channel vertical driver (V-driver). A Precision Timing core allows adjustment of high speed clocks with approximately 600 ps resolution at 36 MHz operation. The on-chip V-driver supports up to 10 channels for use with 3-field (6-phase) CCDs. Two additional vertical outputs can be used with CCDs that contain advanced video readout modes. Voltage levels of up to +15 V and -8 V are supported. The analog front end includes black level clamping, CDS, VGA, and a 12-bit ADC. The timing generator and V-driver provide all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor gate pulses, substrate clock, and substrate bias control. The internal registers are programmed using a 3-wire serial interface. Packaged in an 8 mm x 8 mm CSPBGA, the AD9925 is specified over an operating temperature range of -25C to +85C.
APPLICATIONS
Digital still cameras Digital video camcorders CCD camera modules
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9925
0dB, -2dB, -4dB CCDIN CDS 6dB TO 42dB VGA VREF 12-BIT ADC CLAMP INTERNAL CLOCKS RG H1 TO H4 4 HORIZONTAL DRIVERS DCLK 12 DOUT
PRECISION TIMING GENERATOR
MSHUT STROBE
V1, V2 V3A, V3B V4, V6 V5A, V5B V7, V8 SUBCK
XV1 TO XV8 8 10 V-DRIVER XSG1 TO XSG6 6 VERTICAL TIMING CONTROL INTERNAL REGISTERS SYNC GENERATOR
SL SDI SCK
SUBCK
RSTB
04637-0-001
VSUB
HD
VD SYNC
CLI CLO
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9925 TABLE OF CONTENTS
Specifications..................................................................................... 3 Digital Specifications........................................................................ 4 Vertical Driver Specifications ......................................................... 5 Analog Specifications....................................................................... 6 Timing Specifications....................................................................... 7 Absolute Maximum Ratings............................................................ 8 Package Thermal Characteristics ............................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Terminology .................................................................................... 11 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 13 System Overview ........................................................................ 14 Precision Timing High Speed Timing Generation.................. 15 Horizontal Clamping and Blanking......................................... 18 Horizontal Timing Sequence Example.................................... 21 Vertical Timing Generation...................................................... 22 Vertical Timing Example........................................................... 34 Shutter Timing Control ............................................................. 36 Example of Exposure and Readout of Interlaced Frame........... 41 FG_TRIG Operation.................................................................. 43 Analog Front End Description and Operation ...................... 45 Vertical Driver Signal Configuration ...................................... 47 Power-Up and Synchronization ............................................... 51 Standby Mode Operation .......................................................... 55 Circuit Layout Information....................................................... 57 Serial Interface Timing .............................................................. 59 Complete Listing for Register Bank 1.......................................... 62 Complete Listing for Register Bank 2.......................................... 66 Complete Listing for Register Bank 3.......................................... 87 Outline Dimensions ....................................................................... 94 Ordering Guide .......................................................................... 94
REVISION HISTORY
10/04--Data Sheet Changed from Rev. 0 to Rev. A Changes to Specifications ........................................................................................3 Added Stress Disclaimer..........................................................................................8 Changes to Figure 12................................................................................................13 Changes to Figure 22................................................................................................18 Changes to Figure 55................................................................................................45 Change to DC Restore Section ...............................................................................45 Change to Correlated Double Sampler Section....................................................45 Change to ADC Section...........................................................................................46 Change to Digital Data Outputs Section ...............................................................46 Added Paragraph to Digital Data Outputs Section..............................................46 Changes to Table 34..................................................................................................55 Change to Circuit Layout Information Section....................................................57 Changes to Register Address Bank 1, Bank 2, and Bank 3 Section ...................60 Changes to Table 40..................................................................................................63 Change to Table 46 ...................................................................................................65 Changes to Tables 47-56, 58-73.............................................................................66 4/04--Revision 0: Initial Version
Rev. A | Page 2 of 96
AD9925 SPECIFICATIONS
Table 1.
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGES AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (H1 to H4 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) V-DRIVER SUPPLY VOLTAGES VDVDD (V-Driver Input Logic Supply) VH1, VH2 (V-Driver High Supply for 3-Level Outputs) VM1, VM2 (V-Driver Mid Supply for 3-Level and 2-Level Outputs) VL1, VL2 (V-Driver Low Supply for 3-Level and 2-Level Outputs) POWER DISSIPATION--AFETG Section Only (see Figure 9 for Power Curves) 36 MHz, 3.0 V Supply, 100 pF Load on Each H1 to H4 Output, 20 pF RG Load Standby 1 Mode Standby 2 Mode Standby 3 Mode Power from HVDD Only1 Power from RGVDD Only Power from AVDD Only Power from TCVDD Only Power from DVDD Only Power from DRVDD Only POWER DISSIPATION--V-Driver Section Only (VDVDD, VH, VL) Normal Operation (VH = 15.0 V, VL = -7.5 V)2 Standby 1 Mode2 Standby 2 Mode2 Standby 3 Mode2 MAXIMUM CLOCK RATE (CLI) Min -25 -65 2.7 2.7 2.7 2.7 2.7 2.7 2.7 10.5 -1.0 -10.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 15.0 0.0 -7.5 370 10 10 1 130 10 105 42 57 26 60 70 70 110 36 Typ Max +85 +150 3.6 3.6 3.6 3.6 3.6 3.6 3.6 16.0 +3.0 -6.0 Unit C C V V V V V V V V V V mW mW mW mW mW mW mW mW mW mW mW mW mW mW MHz
1
2
The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = [CLOAD x HVDD x Pixel Frequency] x HVDD. Reducing the H-loading and/or using a lower HVDD supply will reduce the power dissipation. CLOAD is the total capacitance seen by all H-outputs. The power dissipated by the V-driver circuitry depends on the logic states of the inputs as well as actual CCD operation; default dc values are used for each measurement, in each mode of operation. Load conditions are described in the Vertical Driver Specifications section.
Rev. A | Page 3 of 96
AD9925 DIGITAL SPECIFICATIONS
RGVDD = HVDD = DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted. Table 2.
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS (Powered by DVDD, DRVDD) High Level Output Voltage at IOH = 2 mA Low Level Output Voltage at IOL = 2 mA RG and H-DRIVER OUTPUTS (Powered by HVDD, RGVDD) High Level Output Voltage at Maximum Current Low Level Output Voltage at Maximum Current Maximum Output Current (Programmable) Maximum Load Capacitance (for Each Output) Symbol VIH VIL IIH IIL CIN VOH VOL Min 2.1 0.6 10 10 10 VDD - 0.5 0.5 VDD - 0.5 0.5 30 100 Typ Max Unit V V A A pF V V V V mA pF
Rev. A | Page 4 of 96
AD9925 VERTICAL DRIVER SPECIFICATIONS
VDVDD = 3.3 V, VH = 15 V, VM = 0 V, VL = -7.5 V, CL shown in load model, 25C. Table 3.
Parameter 3-LEVEL OUTPUTS (V1, V2, V3A, V3B, V5A, V5B) (Simplified Load Conditions, 6000 pF to Ground) Delay Time, VL to VM and VM to VH Delay Time, VM to VL and VH to VM Rise Time, VL to VM and VM to VH Fall Time, VM to VL and VH to VM Output Currents At -7.25 V At -0.25 V At +0.25 V At +14.75 V 2-LEVEL OUTPUTS (V4, V6, V7, V8) (Simplified Load Conditions, 6000 pF to Ground) Delay Time, VL to VM Delay Time, VM to VL Rise Time, VL to VM Fall Time, VM to VL Output Currents At -7.25 V At -0.25 V SUBCK OUTPUT (Simplified Load Conditions, 1000 pF to Ground) Delay Time, VL to VH Delay Time, VH to VL Rise Time, VL to VH Fall Time, VH to VL Output Currents At -7.25 V At +14.75 V SERIAL VERTICAL CLOCK RESISTANCE GND VERTICAL CLOCK RESISTANCE Symbol Min Typ Max Unit
tPLM, tPMH tPML, tPHM tRLM, tRMH tFML, tFHM 10.0 -5.0 5.0 -7.2
100 200 500 500
ns ns ns ns mA mA mA mA
tPLM tPML tRLM tFML 10.0 -5.0
100 200 500 500
ns ns ns ns mA mA
tPLH tPHL tRLH tFHL 5.4 -4.0 30 10
100 200 200 200
ns ns ns ns mA mA
V-DRIVER INPUT
50%
50%
tRLM, tRMH, tRLH
90% V-DRIVER OUTPUT 10% 90%
tPML, tPHM, tPHL tFML, tFHM, tFHL
10%
04637-0-079
tPLM, tPMH, tPLH
Figure 2. Definition of V-Driver Timing Specifications
Rev. A | Page 5 of 96
AD9925 ANALOG SPECIFICATIONS
AVDD1 = 3.0 V, fCLI = 36 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted. Table 4.
Parameter CDS Allowable CCD Reset Transient Maximum Input Range before Saturation 0 dB CDS Gain (Default Setting) -2 dB CDS Gain -4 dB CDS Gain Maximum CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain (VGA Code 0) Maximum Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level (Code 0) Maximum Clamp Level (Code 255) ANALOG-TO-DIGITAL CONVERTER (ADC) Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 0) Maximum Gain (VGA Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Min Typ 500 1.0 1.25 1.6 +200/-100 1024 Guaranteed 6 42 256 0 255 12 -1.0 Max Unit mV V p-p V p-p V p-p mV Steps Test Conditions/Comments Input Characteristics Definition.1
Positive Offset Definition1
dB dB Steps Measured at ADC Output. LSB LSB Bits LSB V V V Includes Entire Signal Chain.
0.5 Guaranteed 2.0 2.0 1.0
+1.0
5.0 40.5
5.5 41.5 0.1 0.8 50
6.0 42.5
dB dB % LSB rms dB
Gain = (0.0351 x Code) + 5.5 dB. 12 dB Gain Applied. AC Grounded Input, 6 dB Gain Applied. Measured with Step Change on Supply.
1
Input signal characteristics are defined as
1V MAX INPUT SIGNAL RANGE (0dB CDS GAIN)
04637-0-002
500mV TYP RESET TRANSIENT +200mV MAX OPTICAL BLACK PIXEL
Rev. A | Page 6 of 96
AD9925 TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted. Table 5.
Parameter MASTER CLOCK, CLI (Figure 17) CLI Clock Period CLI High/Low Pulse Width Delay from CLI Rising Edge to Internal Pixel Position 0 AFE CLPOB PULSE WIDTH1, 2 (Figure 23 and Figure 29) AFE SAMPLE LOCATION1 (Figure 20) SHP Sample Edge to SHD Sample Edge DATA OUTPUTS (Figure 21 and Figure 22) Output Delay from DCLK Rising Edge, Default Value1 Inhibited Area for DOUTPHASE Edge Location1 Pipeline Delay from SHP/SHD Sampling to DOUT SERIAL INTERFACE (Figure 74 and Figure 75) Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read Symbol tCONV tCLIDLY 2 tS1 tOD tDOUTINH 12.5 Min 27.8 11.2 Typ Max Unit ns ns ns Pixels ns ns SHDLOC + 11 Cycles MHz ns ns ns ns ns
13.9 6 20 13.9 8
16.6
SHDLOC 11 36 10 10 10 10 10
fSCLK tLS tLH tDS tDH tDV
1 2
Parameter is register-programmable. Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Rev. A | Page 7 of 96
AD9925 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter VDVDD VL VH1, VH2 VM1, VM2 AVDD TCVDD HVDD RGVDD DVDD DRVDD RG Output H1 to H4 Output Digital Outputs Digital Inputs SCK, SL, SDATA REFT/REFB, CCDIN Junction Temperature Lead Temperature, 10 s With Respect To VDVSS VDVSS VDVSS VDVSS AVSS TCVSS HVSS RGVSS DVSS DRVSS RGVSS HVSS DVSS DVSS DVSS AVSS Min VDVSS - 0.3 VDVSS - 10 VL - 0.3 VL - 0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max VDVSS +4 VDVSS + 0.3 VL + 27 VL + 27 +3.9 +3.9 +3.9 +3.9 +3.9 +3.9 RGVD D + 0.3 HVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 150 350 Unit V V V V V V V V V V V V V V V V C C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance CSPBGA Package: JA = 40.3C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 8 of 96
AD9925 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 CORNER INDEX AREA 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L
AD9925
TOPVIEW (Not to Scale)
Figure 3. 96-Lead CSPBGA Package Pin Configuration
Table 7. Pin Function Descriptions
Pin No. E1, F2, F3 G2, G3 F1 G1 H1, H2, H3 J2, J3 J1 K1 K2, L2 L3 L4 K3, K4 J4 J5 K5, L5 J6 K6, L7 L6 K7 L8 L9 J7 J8 K8 K9 L10 K11 J11 J10 J9 K10 H9 H11 H10 G10 G11 G9 Mnemonic HVSS HVSS H1 H2 HVDD HVDD H3 H4 RGVSS RG RGVDD TCVDD CLO SYNC TCVSS CLI AVSS CCDIN AVDD REFT REFB MSHUT SUBCK VL VH2 RSTB SL SCK SDI V8 V7 STROBE VM2 V6 V4 V2 VD Type1 P P DO DO P P DO DO P DO P P DO DI P DI P AI P AO AO DO DO P P DI DI DI DI VO2 VO2 DO P VO2 VO2 VO2 DIO Description2 H1 to H4, HL Driver Ground H1 to H4, HL Driver Ground CCD Horizontal Clock 1 CCD Horizontal Clock 2 H1 to H4, HL Driver Supply H1 to H4, HL Driver Supply CCD Horizontal Clock 3 CCD Horizontal Clock 4 RG Driver Ground CCD Reset Gate Clock RG Driver Supply Analog Supply for Timing Core Clock Output for Crystal External System Sync Input Analog Ground for Timing Core Reference Clock Input Analog Ground for AFE CCD Signal Input Analog Supply for AFE Voltage Reference Top Bypass Voltage Reference Bottom Bypass Mechanical Shutter Pulse CCD Substrate Clock (E Shutter) V-Driver Low Supply V-Driver High Supply 2 Reset Bar, Active Low Pulse 3-Wire Serial Load Pulse 3-Wire Serial Clock 3-Wire Serial Data Input CCD Vertical Transfer Clock CCD Vertical Transfer Clock Strobe Pulse V-Driver Mid Supply 2 CCD Vertical Transfer Clock CCD Vertical Transfer Clock CCD Vertical Transfer Clock Vertical Sync Pulse (Input in Slave Mode, Output in Master Mode)
Rev. A | Page 9 of 96
04637-0-003
AD9925
Pin No. F9 F10 F11 E9 D9 E10 D11 C10 C11 B10 B11 A10 A9 C9 B9 B8 A8 B7 A7 B6 A6 C8 C7 C6 C5 B5 A5 A4 B4 A1, A2, A3 B1, B2, B3 C1, C2, C3 C4, D1, D2 D3, E2, E3 D10, E11 L1, L11, A11 Mnemonic HD DVSS DVDD V5B V5A DCLK D0 D1 D2 D3 D4 D5 D6 V3B V3A V1 D7 D8 D9 D10 D11 VM1 VH1 VL DRVDD DRVSS VSUB VDVDD VDVSS NC NC NC NC NC NC NC Type1 DIO P P VO3 VO3 DO DO DO DO DO DO DO DO VO3 VO3 VO3 DO DO DO DO DO P P P P P DO P P Description2 Horizontal Sync Pulse (Input in Slave Mode, Output in Master Mode) Digital Ground Digital Logic Power Supply CCD Vertical Transfer Clock CCD Vertical Transfer Clock Data Clock Output Data Output (LSB) Data Output Data Output Data Output Data Output Data Output Data Output CCD Vertical Transfer Clock CCD Vertical Transfer Clock CCD Vertical Transfer Clock Data Output Data Output Data Output Data Output Data Output (MSB) V-Driver Mid Supply 1 V-Driver High Supply 1 V-Driver Low Supply Data Output Driver Supply Data Output Driver Ground CCD Substrate Bias V-Driver Logic Supply V-Driver Logic Ground Not Internally Connected Not Internally Connected Not Internally Connected Not Internally Connected Not Internally Connected Not Internally Connected Not Internally Connected
1
AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; DIO = Digital Input/Output; P = Power; VO2 = V-Driver Output 2-Level; VO3 = V-Driver Output 3-Level. See Figure 73 for circuit configuration.
2
Rev. A | Page 10 of 96
AD9925 TERMINOLOGY
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9925 from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a Level 1 and is 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = ADC Full Scale/2n codes, where n is the bit resolution of the ADC. For the AD9925, 1 LSB is 0.488 mV. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
Rev. A | Page 11 of 96
AD9925 EQUIVALENT CIRCUITS
AVDD
DVDD
R
300
04637-0-004
100k
AVSS
AVSS
DVSS
Figure 4. CCDIN
Figure 7. SL and RSTB Inputs
DVDD
DRVDD
HVDD OR RGVDD
DATA
RG, H1 TO H4
THREESTATE
DOUT
04637-0-075
THREE-STATE
OUTPUT
04637-0-005
DVSS
DRVSS
HVSS OR RGVSS
Figure 5. Digital Data Outputs
Figure 8. H1 to H4, RG Drivers
DVDD
330
DVSS
Figure 6. Digital Inputs
04637-0-006
Rev. A | Page 12 of 96
04637-0-007
AD9925 TYPICAL PERFORMANCE CHARACTERISTICS
450 VDD = 3.3V 400
POWER DISSIPATION (mW)
40 35 30 25 20 15 10
VDD = 3.0V 350 VDD = 2.7V
NOISE (LSB)
04637-0-084
300
250
200 5 150 18 0
04637-0-083 04637-0-082
24 30 SAMPLE RATE (MHz)
36
0
100
200
300
400 500 600 700 GAIN CODE (Decimal)
800
900 1000
Figure 9. Power vs. Sample Rate
1.0 0.8 0.6 0.4 0.2 5 4 3 2 1
Figure 12. Total Output Noise vs. VGA Gain
LSB
0 -0.2 -0.4 -0.6 -0.8 -1.0
04637-0-080
LSB
0 500 1000 1500 2000 2500 3000 ADC OUTPUT CODE 3500 4000
0 -1 -2 -3 -4 -5 0 500 1000 1500 2000 2500 3000 ADC OUTPUT CODE 3500 4000
Figure 10. Typical DNL Performance
45 40 35 30
GAIN (dB)
Figure 13. Typical INL Performance
25 20 15 10 5 0
04637-0-081
0
100
200
300
400 500 600 700 GAIN CODE (Decimal)
800
900 1000
Figure 11. Typical VGA Gain Curve
Rev. A | Page 13 of 96
AD9925
SYSTEM OVERVIEW
Figure 14 shows the typical system block diagram for the AD9925 used in master mode. The CCD output is processed by the AD9925's AFE circuitr y, which consists of a CDS, VGA, black level clamp, and ADC. The digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9925 from the system microprocessor through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor or external crystal, the AD9925 generates the CCD's horizontal and vertical clocks and internal AFE clocks. External synchronization is provided by a SYNC pulse from the microprocessor, which will reset internal counters and resync the VD and HD outputs. The AD9925 also contains an optional reset pin, RSTB, which may be used to perform an asynchronous hardware reset function. Alternatively, the AD9925 may be operated in slave mode, in which the VD and HD are provided externally from the image processor. In this mode, all AD9925 timing will be synchronized with VD and HD. The H-drivers for H1 to H4 and RG are included in the AD9925, allowing these clocks to be directly connected to the CCD. An H-drive voltage of up to 3.3 V is supported. A high voltage V-driver is also included for the vertical clocks, allowing direct connection to the CCD. The SUBCK and VSUB signals may require external transistors, depending on the CCD used. The AD9925 also includes programmable MSHUT and STROBE outputs, which may be used to trigger mechanical shutter and strobe (flash) circuitry. Figure 15 and Figure 16 show the maximum horizontal and vertical counter dimensions for the AD9925. All internal horizontal and vertical clocking is controlled by these counters to specify line and pixel locations. Maximum HD length is 8192 pixels per line, and maximum VD length is 4096 lines per field.
MAXIMUM COUNTER DIMENSIONS
DOUT CCD CCDIN
V1A, V2, V3A, V3B, V4, V5A, V5B, V6, V7, V8, SUBCK, VSUB
H1 TO H4, RG
AD9925
AFETG + V-DRIVER
DCLK HD, VD CLI
MSHUT STROBE
DIGITAL IMAGE PROCESSING ASIC
13-BIT HORIZONTAL = 8192 PIXELS MAX
SERIAL INTERFACE SYNC RSTB
04637-0-008
12-BIT VERTICAL = 4096 LINES MAX
P
04637-0-009
Figure 15. Vertical and Horizontal Counters Figure 14. Typical System Block Diagram, Master Mode
MAX VD LENGTH IS 4096 LINES
VD
MAX HD LENGTH IS 8192 PIXELS
HD
CLI
Figure 16. Maximum VD/HD Dimensions
Rev. A | Page 14 of 96
04637-0-010
AD9925
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9925 generates high speed timing signals using the flexible Precision Timing core. This core is the foundation that generates the timing used for both the CCD and the AFE: the reset gate (RG), horizontal drivers H1 to H4, and the SHP/SHD sample clocks. The unique architecture provides precise control over the horizontal CCD readout and the AFE correlated double sampling, allowing the system designer to optimize image quality. The high speed timing of the AD9925 operates the same in either master or slave mode configuration. For more information on synchronization and pipeline delays, see the Power-Up and Synchronization section. crystal can be placed between the CLI and CLO pins to generate the master clock for the AD9925. For more information on using a crystal, see Figure 72.
High Speed Clock Programmability
Figure 18 shows how the high speed clocks RG, H1 to H4, SHP, and SHD are generated. The RG pulse has programmable rising and falling edges and may be inverted using the polarity control. The horizontal clocks, H1 and H3, have programmable rising and falling edges and polarity control. The H2 and H4 clocks are always inverses of H1 and H3, respectively. Table 8 summarizes the high speed timing registers and their parameters. Figure 19 shows the typical 2-phase H-clock arrangement in which H3 and H4 are programmed for the same edge location as H1 and H2. The edge location registers are 6 bits wide, but there are only 48 valid edge locations available. Therefore, the register values are mapped into four quadrants, with each quadrant containing 12 edge locations. Table 9 shows the correct register values for the corresponding edge locations.
Timing Resolution
The Precision Timing core uses a 13 master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 17 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Using a 20 MHz CLI frequency, the edge resolution of the Precision Timing core is 1 ns. If a 1x system clock is not available, it is also possible to use a 2x reference clock by programming the CLIDIVIDE register (Addr x30). The AD9925 will then internally divide the CLI frequency by two. The AD9925 also includes a master clock output, CLO, which is the inverse of CLI. This output can be used as a crystal driver. A
POSITION CLI
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
tCLIDLY
1 PIXEL PERIOD
Figure 17. High Speed Clock Resolution from CLI Master Clock Input
Rev. A | Page 15 of 96
04637-0-011
NOTES 1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. 2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY = 6ns TYP).
AD9925
3 CCD SIGNAL 1 RG 2 4
5 H1
6
H2 7 H3 8
H4 PROGRAMMABLE CLOCK POSITIONS: 1. RG RISING EDGE. 2. RG FALLING EDGE. 3. SHP SAMPLE LOCATION. 4. SHD SAMPLE LOCATION. 5. H1 RISING EDGE POSITION AND 6: H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1). 7. H3 RISING EDGE POSITION AND 8: H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3).
Figure 18. High Speed Clock Programmable Locations
Figure 20 shows the default timing locations for all of the high speed clock signals.
Digital Data Outputs
The AD9925 data output and DCLK phase are programmable using the DOUTPHASE register (Addr x37, Bits [5:0]). Any edge from 0 to 47 may be programmed, as shown in Figure 21. Normally, the DOUT and DCLK signals will track in phase, based on the DOUTPHASE register contents. The DCLK output phase can also be held fixed with respect to the data outputs by changing the DCLKMODE register high (Addr x37, Bit [6]). In this mode, the DCLK output will remain at a fixed phase equal to CLO (the inverse of CLI), while the data output phase is still programmable. There is a fixed output delay from the DCLK rising edge to the DOUT transition, called tOD. This delay can be programmed to four values between 0 ns and 12 ns by using the DOUTDELAY register (Addr x37, Bits [8:7]). The default value is 8 ns. The pipeline delay through the AD9925 is shown in Figure 22. After the CCD input is sampled by SHD, there is an 11 cycle delay until the data is available.
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9925 features on-chip output drivers for the RG and H1 to H4 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver and RG current can be adjusted for optimum rise/fall time with a particular load by using the DRVCONTROL register (Addr x35). The 3-bit drive setting for each output is adjustable in 4.1 mA increments, with the minimum setting of 0 equal to OFF or three-state and the maximum setting of 7 equal to 30.1 mA. As shown in Figure 18, Figure 19, and Figure 20, the H2 and H4 outputs are inverses of H1 and H3, respectively. The H1/H2 crossover voltage is approximately 50% of the output swing. The crossover voltage is not programmable.
Table 8. Timing Core Register Parameters for H1, H3, RG, SHP/SHD
Parameter Polarity Positive Edge Negative Edge Sampling Location Drive Strength Length 1b 6b 6b 6b 3b Range High/Low 0 to 47 Edge Location 0 to 47 Edge Location 0 to 47 Edge Location 0 to 47 Current Steps Description Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion) Positive Edge Location for H1, H3, and RG Negative Edge Location for H1, H3, and RG Sampling Location for Internal SHP and SHD Signals Drive Current for H1 to H4 and RG Outputs (4.1 mA per Step)
Rev. A | Page 16 of 96
04637-0-012
AD9925
CCD SIGNAL
RG
H1/H3
H2/H4
04637-0-013
NOTE 1. USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.
Figure 19. 2-Phase H-Clock Operation
Table 9. Precision Timing Edge Locations
Quadrant I II III IV Edge Location (Dec) 0 to 11 12 to 23 24 to 35 36 to 47 Register Value (Dec) 0 to 11 16 to 27 32 to 43 48 to 59 Register Value (Bin) 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011
POSITION
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
PIXEL PERIOD RGr[0] RG RGf[12]
Hr[0] H1/H3
Hf[24]
H2/H4
SHP[24] CCD SIGNAL
tS1
SHD[48]
NOTES 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. 2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
Figure 20. High Speed Timing Default Locations
Rev. A | Page 17 of 96
04637-0-014
AD9925
P[0] PIXEL PERIOD P[12] P[24] P[36] P[48] = P[0]
DCLK
tOD
DOUT
NOTES 1. DATA OUTPUT (DOUT) AND DCLK PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS. 3. OUTPUT DELAY (tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
Figure 21. Digital Output Phase Adjustment
CLI
tCLIDLY
N-1 CCDIN SAMPLE PIXEL N SHD (INTERNAL) ADC DOUT (INTERNAL) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13
04637-0-015
N - 13
N - 12
N - 11
N - 10
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
N+2
tDOUTINH
DCLK PIPELINE LATENCY = 11 CYCLES DOUT N - 13 N - 12 N - 11 N - 10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N N+1 N+2
Figure 22. Digital Data Output Pipeline Delay
HORIZONTAL CLAMPING AND BLANKING
The AD9925's horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK during the different regions of each field. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout, which accommodates the different image transfer timing and high speed line shifts. A separate pattern for CLPOB and PBLK may be programmed for every 10 vertical sequences. As described in the Vertical Timing Generation section, up to 10 separate vertical sequences can be created, each containing a unique pulse pattern for CLPOB and PBLK. Figure 37 shows how the sequence change positions divide the readout field into different regions. A different vertical sequence can be assigned to each region, allowing the CLPOB and PBLK signals to be changed accordingly with each change in the vertical timing.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as shown in Figure 23. These two signals are independently programmed using the registers in Table 10. SPOL is the start polarity for the signal, and TOG1 and TOG2 are the first and second toggle positions of the pulse. Both signals are active low and should be programmed accordingly.
CLPOB Masking Area
Additionally, the AD9925 allows the CLPOB signal to be disabled during certain lines in the field without changing any of the existing CLPOB pattern settings. There are two ways to use CLPOB masking. First, the six CLPOBMASK registers can be used
Rev. A | Page 18 of 96
04637-A-001
NOTES 1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0. 2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION. 3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BY tDOUTINH, WHICH IS EQUAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT THE 11 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED FOR THE DOUTPHASE LOCATION. 4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC. 5. RECOMMENDED VALUE FOR tOD (DOUT DLY) IS 4ns. 6. THE DOUT LATCH CAN BE BYPASSED USING REGISTER 0x03, BIT [4] = 1, SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT THE DOUT PINS. THIS CONFIGURATION IS RECOMMENDED IF ADJUSTABLE DOUT PHASE IS NOT REQUIRED.
AD9925
to specify six individual lines within the field. These lines will not contain an active CLPOB pulse. CLPMASKTYPE is set low for this mode of operation. Second, the CLPMASK registers can be used to specify blocks of adjacent lines. The CLPMASK start and end line values are programmed to specify the starting and ending lines in the field, where the CLPOB patterns will be ignored. There are three sets of start and end values, allowing up to three CLPOB masking areas to be created. CLPMASKTYPE is set high for this mode of operation. The CLPOB masking registers are not specific to a certain vertical sequence; they are always active for any existing field of timing. To disable the CLPOB masking feature, these registers should be set to the maximum value of 0xFFF (default value).
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 24 is similar to CLPOB and PBLK, but there is no start polarity control. Only the toggle positions are used to designate the start and the stop positions of the blanking period. Additionally, there is a polarity control HBLKMASK that designates the polarity of the horizontal clock signals H1 to H4 during the blanking period. Setting HBLKMASK high will set H1 = H3 = Low and H2 = H4 = High during the blanking, as shown in Figure 25. As with the CLPOB and PBLK signals, HBLK registers are available in each vertical sequence, which allow different blanking signals to be used with different vertical timing sequences. One additional feature is the ability to enable the H3/H4 signals to remain active during HBLK. To do this, set register Bit D6 in Addr 0xE7 equal to 1. This feature is useful if the H3 output is used to drive the HL (last horizontal gate) input of the CCD.
Table 10. CLPOB and PBLK Pattern Registers
Register SPOL TOG1 TOG2 CLPOBMASK Length 1b 12 b 12 b 12 b Range High/Low 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Line Location Description Starting Polarity of CLPOB/PBLK for Vertical Sequence 0 to 9. First Toggle Position within Line for Vertical Sequence 0 to 9. Second Toggle Position within Line for Vertical Sequence 0 to 9. CLPOBMASK0 through CLPOBMASK5 specify six individual lines in the field for the CLPOB pulse to be temporarily disabled. These registers can also be used to specify three ranges of adjacent lines, rather than six individual lines. When set low (default), the CLPOBMASK registers select individual lines in the field to disable the CLPOB pulse. When set high, the range masking is enabled, allowing up to three blocks of adjacent lines to have the CLPOB signal masked. CLPOBMASK0 and CLPOBMASK1 are the start/end of the first block of lines, CLPOBMASK2 and CLPOBMASK3 are the start/end of the second block, and CLPOBMASK4 and CLPOBMASK5 are the start/end of the third block.
CLPMASKTYPE
1b
High/Low
HD
2 CLPOB 1 PBLK ACTIVE
3 ACTIVE
NOTES PROGRAMMABLE SETTINGS: 1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW). 2. FIRST TOGGLE POSITION. 3. SECOND TOGGLE POSITION.
Figure 23. Clamp and Preblank Pulse Placement
Rev. A | Page 19 of 96
04637-0-017
AD9925
Table 11. HBLK Pattern Registers
Register HBLKMASK H3HBLKOFF HBLKALT Length 1b 1b 2b Range High/Low High/Low 0 to 3 Alternation Mode Description Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High). Addr 0xE7, Bit [6]. Set = 1 to keep H3/H4 active during HBLK pulse. Normal set to 0. Enables Odd/Even Alternation of HBLK Toggle Positions. 0 = Disable Alternation. 1 = TOG1 to TOG2 Odd, TOG3 to TOG6 Even. 2 = 3 = TOG1to TOG2 Even, TOG3 to TOG6 Odd. First Toggle Position within Line for Each Vertical Sequence 0 to 9. Second Toggle Position within Line for Each Vertical Sequence 0 to 9. Third Toggle Position within Line for Each Vertical Sequence 0 to 9. Fourth Toggle Position within Line for Each Vertical Sequence 0 to 9. Fifth Toggle Position within Line for Each Vertical Sequence 0 to 9. Sixth Toggle Position within Line for Each Vertical Sequence 0 to 9.
HBLKTOG1 HBLKTOG2 HBLKTOG3 HBLKTOG4 HBLKTOG5 HBLKTOG6
12 b 12 b 12 b 12 b 12 b 12 b
0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location
Generating Special HBLK Patterns
There are six toggle positions available for HBLK. Normally, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions may be used to generate special HBLK patterns, as shown in Figure 26. The pattern in this example uses all six toggle positions to generate two extra groups of pulses during the HBLK interval. By changing the toggle positions, different patterns can be created.
Generating HBLK Line Alternation
One further feature of the AD9925 is the ability to alternate different HBLK toggle positions on odd and even lines. This may be used in conjunction with vertical pattern odd/even alternation or on its own. When a 1 is written to the HBLKALT register, TOG1 and TOG2 are used on odd lines, while TOG3 to TOG6 are used on even lines. Writing a 2 to the HBLKALT register gives the opposite result: TOG1 and TOG2 are used on even lines, while TOG3 to TOG6 are used on odd lines. See the Vertical Timing Generation section for more information.
HD
1 HBLK BLANK
2 BLANK
04637-0-018
PROGRAMMABLE SETTINGS: 1. FIRST TOGGLE POSITION = START OF BLANKING. 2. SECOND TOGGLE POSITION = END OF BLANKING.
Figure 24. Horizontal Blanking (HBLK) Pulse Placement
HD
HBLK
H1/H3
H1/H3
H2/H4
04637-0-019
NOTE 1. THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
Figure 25. HBLK Masking Control
Rev. A | Page 20 of 96
AD9925
TOG1 TOG2 TOG3 TOG4 TOG5 TOG6
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS
Figure 26. Generating Special HBLK Patterns
Increasing H-Clock Width during HBLK
The AD9925 will also allow the H1 to H4 pulse width to be increased during the HBLK interval. The H-clock pulse width can increase by reducing the H-clock frequency (see Figure 27). The HBLKWIDTH register, at Bank 1 Address 0x38, is a 3-bit register that allows the H-clock frequency to be reduced by 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequency will only occur for H1 to H4 pulses that are located within the HBLK area. Table 12. HBLK Width Register
Register HBLKWIDTH Length 3b Range 1 to 1/14 Description Controls H1 to H4 width during HBLK as a fraction of pixel rate 0: same frequency as pixel rate 1: 1/2 pixel frequency, i.e., doubles the H1 to H4 pulse width 2: 1/4 pixel frequency 3: 1/6 pixel frequency 4: 1/8 pixel frequency 5: 1/10 pixel frequency 6: 1/12 pixel frequency 7: 1/14 pixel frequency
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 28 shows an example CCD layout. The horizontal register contains 28 dummy pixels, which will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and 2 at the back of the readout. The horizontal direction has 4 OB pixels in the front and 48 in the back. Figure 29 shows the basic sequence layout to be used during the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB signals. PBLK is optional and is often used to blank the digital outputs during the noneffective CCD pixels. HBLK is used during the vertical shift interval. The HBLK, CLPOB, and PBLK parameters are programmed in the vertical sequence registers. More elaborate clamping schemes may be used, such as adding in a separate sequence to clamp during the entire shield OB lines. This requires configuring a separate vertical sequence for reading out the OB lines.
HBLK
H1/H3 1/FPIX 2 x (1/FPIX)
H2/H4
04637-0-070
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN), 1/4, 1/6, 1/8, 1/10, 1/12, OR 1/14 USING HBLKWIDTH REGISTER
Figure 27. Generating Wide H-Clock Pulses during HBLK Interval
Rev. A | Page 21 of 96
04637-0-020
AD9925
2 VERTICAL OB LINES V EFFECTIVE IMAGE AREA 10 VERTICAL OB LINES
H 4 OB PIXELS HORIZONTAL CCD REGISTER
04637-0-021
48 OB PIXELS
28 DUMMY PIXELS
Figure 28. Example CCD Configuration
OPTICAL BLACK HD
OB
CCDIN
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
OPTICAL BLACK
VERT SHIFT
SHP SHD H1/H3 H2/H4
HBLK PBLK CLPOB
05637-0-022
Figure 29. Horizontal Sequence Example
VERTICAL TIMING GENERATION
The AD9925 provides a very flexible solution for generating vertical CCD timing and can support multiple CCDs and different system architectures. The vertical transfer clocks XV1 to XV8 are used to shift each line of pixels into the horizontal output register of the CCD. The AD9925 allows these outputs to be individually programmed into various readout configurations, using a 4-step process. Figure 30 shows an overview of how the vertical timing is generated in four steps. First, the individual pulse patterns for XV1 to XV8 are created by using the vertical pattern group registers.
Second, the vertical pattern groups are used to build the sequences, where additional information is added. Third, the readout for an entire field is constructed by dividing the field into different regions and then assigning a sequence to each region. Each field can contain up to seven different regions to accommodate the different steps of the readout, such as high speed line shifts and unique vertical line transfers. Up to six different fields may be created. Finally, the MODE register allows the different fields to be combined into any order for various readout configurations.
Rev. A | Page 22 of 96
AD9925
1
CREATE THE VERTICAL PATTERN GROUPS (MAXIMUM OF 10 GROUPS) XV1 XV2 XV3 VPAT 0 XV4 XV5 XV6 VERTICAL SEQUENCE 0 XV4 (VPAT0, 1 REP) XV5 XV6
2
BUILD THE VERTICAL SEQUENCES BY ADDING LINE START POSITION, # OF REPEATS, AND HBLK/CLPOB PULSES (MAXIMUM OF 10 VERTICAL SEQUENCES) XV1 XV2 XV3
XV1 XV1 XV2 XV3 VPAT 9 XV4 XV5 XV6 VERTICAL SEQUENCE 1 (VPAT9, 2 REP) XV4 XV5 XV6 XV2 XV3
XV1 XV2 XV3 VERTICAL SEQUENCE 2 (VPAT9, N REP) XV4 XV5 XV6
3
USE THE MODE REGISTER TO CONTROL WHICH FIELDS ARE USED, AND IN WHAT ORDER (MAXIMUM OF 7 FIELDS MAY BE COMBINED IN ANY ORDER)
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS AND ASSIGNING A DIFFERENT VERTICAL SEQUENCE TO EACH (MAXIMUM OF 7 REGIONS IN EACH FIELD) (MAXIMUM OF 6 FIELDS) FIELD 0
3
FIELD 0
FIELD 1
FIELD 2 REGION 0: USE VERTICAL SEQUENCE 2 REGION 0: USE V-SEQUENCE 3 REGION 1: USE VERTICAL SEQUENCE 0 REGION 0: USE V-SEQUENCE 3 REGION 2:REGION 1: USE V-SEQUENCE 2 USE VERTICAL SEQUENCE 3 REGION 1: USE V-SEQUENCE 2
FIELD 3
FIELD 4
REGION 3: USE VERTICAL SEQUENCE 0 REGION 2: USE V-SEQUENCE 1 FIELD 5 FIELD 1 FIELD 4 FIELD 2 REGION 2: USE V-SEQUENCE 1 REGION 4: USE VERTICAL SEQUENCE 2 FIELD 1 FIELD 2
04637-0-023
Figure 30. Summary of Vertical Timing Generation
Rev. A | Page 23 of 96
AD9925
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns for each XV1 to XV6 output signal. Table 13 summarizes the registers available for generating each of the 10 vertical pattern groups. The start polarity (VPOL) determines the starting polarity of the vertical sequence and can be programmed high or low for each XV1 to XV6 output. The first, second, and third toggle positions (XVTOG1, XVTOG2, and XVTOG3) are the pixel locations within the line where the pulse transitions. A fourth toggle position (XVTOG4) is also available for vertical pattern groups 8 and 9. All toggle positions are 12-bit values, allowing their placement anywhere in the horizontal line. A Table 13. Vertical Pattern Group Registers
Register XVPOL XVTOG1 XVTOG2 XVTOG3 XVTOG4 VPATLEN FREEZE1 RESUME1 FREEZE2 RESUME2 Length 1b 12 b 12 b 12 b 12 b 12 b 12 b 12 b 12 b 12 b Range High/Low 0 to 4096 Pixel Location 0 to 4096 Pixel Location 0 to 4096 Pixel Location 0 to 4096 Pixel Location 0 to 4096 Pixels 0 to 4096 Pixel Location 0 to 4096 Pixel Location 0 to 4096 Pixel Location 0 to 4096 Pixel Location Description Starting Polarity of Each XV Output First Toggle Position within Line for Each XV Output Second Toggle Position within Line for Each XV Output Third Toggle Position within Line for Each XV Output Fourth Toggle Position, Only Available in Vertical Pattern Groups 8 and 9 and Also in XV7 and XV8 Vertical Pattern Groups Total Length of Each Vertical Pattern Group Holds the XV Outputs at Their Current Levels (Static DC) Resumes Operation of the XV Outputs to Finish Their Pattern Holds the XV Outputs at Their Current Levels (Static DC) Resumes Operation of the XV Outputs to Finish Their Pattern
separate register, VPATSTART, specifies the start position of the vertical pattern groups within the line (see the Vertical Sequences (VSEQ) section). The VPATLEN register designates the total length of the vertical pattern group, which determines the number of pixels between each of the pattern repetitions when repetitions are used (see the Vertical Sequences (VSEQ) section). Additional VPAT groups are provided in Register Bank 3 for the XV7 and XV8 outputs. This allows the AD9925 to remain backward-compatible with the AD9995 register settings while still providing additional flexibility with XV7 and XV8 for new CCDs.
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS
HD
4
XV1
1 2 3
XV2
1 2 3
XV6
1 2 3
PROGRAMMABLE SETTINGS FOR EACH VERTICAL PATTERN: 1. START POLARITY. 2. FIRST TOGGLE POSITION. 3. SECOND TOGGLE POSITION (THIRD TOGGLE POSITION ALSO AVAILABLE, FOURTH TOGGLE POSITION AVAILABLE FOR VERTICAL PATTERN GROUPS 8 AND 9). 4. TOTAL PATTERN LENGTH FOR ALL XV OUTPUTS.
Figure 31. Vertical Pattern Group Programmability
Rev. A | Page 24 of 96
04637-0-024
AD9925
Masking Using FREEZE/RESUME Registers
As shown in Figure 33, the FREEZE/RESUME registers are used to temporarily mask the XV outputs. The pixel locations to begin the masking (FREEZE) and end the masking (RESUME) create an area in which the vertical toggle positions are ignored. At the pixel location specified in the FREEZE register, the XV outputs will be held static at their current dc state, high or low. The XV outputs are held until the pixel location specified by the RESUME register is reached, at which point the signals will continue with any remaining toggle positions. Two sets of FREEZE/RESUME registers are provided, allowing the vertical outputs to be interrupted twice in the same line. The FREEZE and RESUME positions are programmed in the vertical pattern group registers, but are enabled separately using the VMASK registers. The VMASK registers are described in the Vertical Sequences (VSEQ) section.
HD NO MASKING AREA
XV1
XV8
Figure 32. No Vertical Masking
HD
FREEZE
MASKING AREA FOR XV1 TO XV8
RESUME
XV1
XV8 NOTES 1. ALL TOGGLE POSITIONS WITHIN THE FREEZE/RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING. 2. TWO SEPARATE MASKING AREAS ARE AVAILABLE FOR EACH VPAT GROUP, USING FREEZE1/RESUME1 AND FREEZE2/RESUME2 REGISTERS.
04637-0-026
Figure 33. Vertical Masking Using the FREEZE/RESUME Registers
Rev. A | Page 25 of 96
04637-0-025
AD9925
Hold Area Using FREEZE/RESUME Registers
The FREEZE/RESUME registers can also be used to create a hold area, in which the XV outputs are temporarily held and then later continued starting at the point where they were held. As shown in Figure 34 and Figure 35, this is different than the VMASK, because the XV outputs continue from where they stopped rather than continuing from where they would have been. The hold area temporarily stops the pixel counter for the XV outputs, while the v-masking allows the counter to continue during the masking area. XV7 and XV8 may or may not use the hold area, as shown in Figure 34 and Figure 35. The hold operation is controlled in the Bank 3 vertical sequence registers, described in the Vertical Sequences (VSEQ) section.
HD FREEZE
HOLD AREA FOR XV1-XV6
RESUME
XV1
XV6
XV7 NO HOLD AREA FOR XV7-XV8
04637-0-072
04637-0-028
XV8
NOTES 1. WHEN HOLD = 1 FOR ANY V-SEQUENCE, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA BOUNDRIES. 2. WHEN XV78HOLDEN = 0, XV7 AND XV8 DO NOT USE THE HOLD AREA, ONLY XV1-XV6. H-COUNTER FOR XV1-XV6 WILL STOP DURING HOLD AREA.
Figure 34. Vertical Hold Area Using the FREEZE/RESUME Registers
HD
HOLD AREA FREEZE FOR XV1 TO XV8 RESUME
XV1
XV6
XV7
XV8 NOTES 1. WHEN HOLD = 1 FOR ANY VERTICAL SEQUENCE, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA BOUNDRIES. 2. WHEN XV78HOLDEN = 1, XV7 AND XV8 ALSO USE THE HOLD AREA. H-COUNTER FOR XV1 TO XV8 WILL STOP DURING HOLD AREA.
Figure 35. Apply Hold Area to XV7 and XV8
Rev. A | Page 26 of 96
AD9925
Vertical Sequences (VSEQ)
The vertical sequences are created by selecting one of the 10 vertical pattern groups and adding repeats, the start position, and horizontal clamping and blanking information. Up to 10 vertical sequences may be programmed, each using the registers shown in Table 14. Figure 36 shows how the different registers are used to generate each vertical sequence. The VPATSEL register selects which vertical pattern group will be used in a given vertical sequence. The basic vertical pattern group can have repetitions added for high speed line shifts or line binning by using the VPATREPO and VPATREPE registers. Generally, the same number of repetitions is programmed into both registers, but if a different number of repetitions is required on odd and even lines, separate values may be used for each register (see the Generating Line Alternation for Vertical Sequence and HBLK section). The VPATSTART register specifies the pixel location where the vertical pattern group will start. The VMASK register is used in conjunction with the FREEZE/ RESUME registers to enable optional masking of the vertical outputs. Either or both of the FREEZE1/RESUME1 and FREEZE2/RESUME2 registers can be enabled using the VMASK register. The line length (in pixels) is programmable using the HDLEN registers. Each vertical sequence can have a different line length to accommodate the various image readout techniques. The maximum number of pixels per line is 8192. Note that the 13th bit (MSB) of the line length is located in a separate register. Also note that the last line of the field is separately programmable using the HDLAST register, located in the field register section. Additional vertical sequences are provided in Register Bank 3 for the XV7 and XV8 outputs. This allows the AD9925 to remain backward-compatible with the AD9995 register settings while still providing additional flexibility with XV7 and XV8 for new CCDs. As described in the Hold Area Using FREEZE/RESUME Registers section, the hold registers in Bank 3 are used to specify a hold area instead of vertical masking. The FREEZE/RESUME registers are used to define the hold area. The XV78HOLDEN registers are used to specify whether XV7 and XV8 will use the hold area or not.
Table 14. Vertical Sequence Registers (See Table 10 and Table 11 for the HBLK, CLPOB, and PBLK registers)
Register VPATSEL VMASK Length 4b 2b Range 0 to 9 Vertical Pattern Group No. 0 to 3 Mask Mode Description Selected Vertical Pattern Group for Each Vertical Sequence. Enables the Masking of V1 to V6 Outputs at the Locations Specified by the FREEZE/RESUME Registers. 0 = No Mask. 1 = Enable Freeze1/Resume1. 2 = Enable Freeze2/Resume2. 3 = Enable Both 1 and 2. Number of Repetitions for the Vertical Pattern Group for Odd Lines. If no odd/even alternation is required, set equal to VPATREPE. Number of Repetitions for the Vertical Pattern Group for Even Lines. If no odd/even alternation is required, set equal to VPATREPO. Start Position for the Selected Vertical Pattern Group. HD Line Length for Lines in Each Vertical Sequence. Note that 13th bit (MSB) of the line length is located in a separate register to maintain compatibility with AD9995.
VPATREPO VPATREPE VPATSTART HDLEN
12 b 12 b 12 b 13 b
0 to 4095 Number of Repeats 0 to 4095 Number of Repeats 0 to 4095 Pixel Location 0 to 8191 Number of Pixels
HOLD1
1b
High/Low
Enable Hold Area Instead of Vertical Masking, Using FREEZE/RESUME Registers.
Enable XV7 and XV8 to Use Hold Area. 0 = Disable. 1 = Enable.
XV78HOLDEN1
1b
High/Low
1
Located in Bank 3, vertical sequence registers for XV7 and XV8.
Rev. A | Page 27 of 96
AD9925
1
HD 2 3 XV1 TO XV6 VERTICAL PATTERN GROUP CLPOB PBLK 6 PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE: 1. START POSITION IN THE LINE OF SELECTED VERTICAL PATTERN GROUP. 2. HD LINE LENGTH. 3. VERTICAL PATTERN SELECT (VPATSEL) TO SELECT ANY VERTICAL PATTERN GROUP. 4. NUMBER OF REPETITIONS OF THE VERTICAL PATTERN GROUP (IF NEEDED). 5. START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS. 6. MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL. 5 4 VPAT REP 2 4 VPAT REP 3
HBLK
Figure 36. Vertical Sequence Programmability
Rev. A | Page 28 of 96
04637-0-029
AD9925
Complete Field: Combining Vertical Sequences
After the vertical sequences have been created, they are combined to create different readout fields. A field consists of up to seven different regions, and within each region, a different vertical sequence can be selected. Figure 37 shows how the sequence change positions (SCP) designate the line boundary for each region, and how the VSEQSEL registers select which vertical sequence is used during each region. Registers to control the XSG outputs are also included in the field registers. Table 15 summarizes the registers used to create the different fields. Up to six different fields can be preprogrammed using the field registers. The VEQSEL registers, one for each region, select which of the 10 vertical sequences will be active during each region. The SWEEP registers are used to enable the sweep mode during any region. The MULTI registers are used to enable the multiplier mode during any region. The SCP registers create the line Table 15. Field Registers
Register VSEQSEL SWEEP MULTI SCP VDLEN HDLAST VPATSECOND SGMASK SGPATSEL SGLINE1 SGLINE2 Length 4b 1b 1b 12 b 12 b 13 b 4b 6b 12 b 12 b 12 b Range 0 to 9 V Sequence Number High/Low High/Low 0 to 4095 Line Number 0 to 4095 Number of Lines 0 to 8191 Number of Pixels 0 to 9 Vertical Pattern Group Number High/Low, Each XSG 0 to 3 Pattern Number, Each XSG 0 to 4095 Line Number 0 to 4095 Line Number Description Selected Vertical Sequence for Each Region in the Field. Enables Sweep Mode for Each Region, When Set High. Enables Multiplier Mode for Each Region, When Set High. Sequence Change Position for Each Region. Total Number of Lines in Each Field. Length in Pixels of the Last HD Line in Each Field. The13th bit (MSB) is located in a separate register to maintain compatibility with the AD9995. Selected Vertical Pattern Group for Second Pattern Applied During SG Line. Set High to Mask Each Individual XSG Output. XSG1 [0], XSG2 [1], XSG3 [2], XSG4 [3], XSG5 [4], XSG6 [5]. Selects the SG Pattern Number for Each XSG Output. XSG1 [1:0], XSG2 [3:2], XSG3 [5:4], XSG4 [7:6], XSG5 [9:8], XSG6 [11:10]. Selects the Line in the Field Where the SG Signals Are Active. Selects a Second Line in the Field to Repeat the SG Signals.
boundaries for each region. The VDLEN register specifies the total number of lines in the field. The total number of pixels per line (HDLEN) is specified in the vertical sequence registers, but the HDLAST register specifies the number of pixels in the last line of the field. Note that the 13th bit (MSB) of the last line length is located in a separate register. During the sensor gate (SG) line, the VPATSECOND register is used to add a second vertical pattern group to the XV outputs. The SGMASK register is used to enable or disable each individual VSG output. There is a single bit for each XSG output, setting the bit high will mask the output and setting it low will enable the output. The SGPAT register assigns one of the four different SG patterns to each VSG output. The individual SG patterns are created separately using the SG pattern registers. The SGLINE1 register specifies which line in the field will contain the XSG outputs. The optional SGLINE2 register allows the same SG pulses to be repeated on a different line.
SCP 1
SCP 2
SCP 3
SCP 4
SCP 5
SCP 6
VD REGION 0 HD REGION 1 REGION 2 REGION 3 REGION 4 REGION 5 REGION 6
XV1 TO XV6
VSEQSEL0
VSEQSEL1 SGLINE
VSEQSEL2
VSEQSEL3
VSEQSEL4
VSEQSEL5
VSEQSEL6
XSG FIELD SETTINGS: 1. SEQUENCE CHANGE POSITIONS (SCP1 TO SCP6) DEFINE EACH OF THE SEVEN REGIONS IN THE FIELD. 2. VSEQSEL0 TO VSEQSEL6 SELECTS THE DESIRED VERTICAL SEQUENCE (0-9) FOR EACH REGION. 3. SGLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD WILL CONTAIN THE SENSOR GATE PULSE(S).
04637-0-030
Figure 37. Complete Field Is Divided into Regions
Rev. A | Page 29 of 96
AD9925
Generating Line Alternation for Vertical Sequence and HBLK
During low resolution readout, some CCDs require a different number of vertical clocks on alternate lines. The AD9925 can support this by using the VPATREPO and VPATREPE registers. This allows a different number of VPAT repetitions to be programmed on odd and even lines. Note that only the number of repeats can be different in odd and even lines, but the VPAT group remains the same. Additionally, the HBLK signal can also be alternated for odd and even lines. When the HBLKALT register is set high, the HBLK TOG1 and HBLK TOG2 positions will be used on odd lines, and the HBLK TOG3 to HBLK TOG6 positions will be used on even lines. This allows the HBLK interval to be adjusted on odd and even lines if needed. Figure 38 shows an example of a VPAT repetition alternation and a HBLK alternation used together. It is also possible to use the VPAT and HBLK alternation separately.
HD VPATREPO = 2 XV1 VPATREPE = 5 VPATREPO = 2
Second Vertical Pattern Group during VSG Active Line
Most CCDs require additional vertical timing during the sensor gate (SG) line. The AD9925 supports the option to output a second vertical pattern group for XV1 to XV8 during the line when the sensor gates XSG1 to XSG6 are active. Figure 39 shows a typical SG line that includes two separate sets of vertical pattern group for XV1 to XV6. The vertical pattern group at the start of the SG line is selected in the same manner as the other regions, using the appropriate VSEQSEL register. The second vertical pattern group, unique to the SG line, is selected using the VPATSECOND register, located with the field registers. The start position of the second VPAT group uses the VPATLEN register from the selected VPAT registers. Because the VPATLEN register is used as the start position and not as the VPAT length, it is not possible to program multiple repetitions for the second VPAT group.
XV2
XV6
TOG1 HBLK
TOG2
TOG3
TOG4
TOG1
TOG2
NOTES 1. THE NUMBER OF REPEATS FOR THE VERTICAL PATTERN GROUP MAY BE ALTERNATED ON ODD AND EVEN LINES. 2. THE HBLK TOGGLE POSITIONS MAY BE ALTERNATED BETWEEN ODD AND EVEN LINES, IN ORDER TO GENERATE DIFFERENT HBLK PATTERNS FOR ODD/EVEN LINES.
Figure 38. Odd/Even Line Alteration of VPAT Repetitions and HBLK Toggle Positions
HD
START POSITION FOR SECOND VPAT GROUP USES VPATLEN REGISTER
XSG
XV1
XV2
SECOND VPAT GROUP
Figure 39. Example of Second VPAT Group during Sensor Gate Line
Rev. A | Page 30 of 96
04637-0-032
XV6
04637-0-031
AD9925
Sweep Mode Operation
The AD9925 contains an additional mode of vertical timing operation called sweep mode. This mode is used to generate a large number of repetitive pulses that span across multiple HD lines. One example of where this mode is needed is at the start of the CCD readout operation. At the end of the image exposure, but before the image is transferred by the sensor gate pulses, the vertical interline CCD registers should be free of all charge. This can be accomplished by quickly shifting out any charge using a long series of pulses from the XV outputs. Depending on the vertical resolution of the CCD, up to two or three thousand clock cycles will be needed to shift the charge out of each vertical CCD line. This operation will span across multiple HD line lengths. Normally, the AD9925 vertical timing must be contained within one HD line length, but when sweep mode is enabled, the HD boundaries will be ignored until the region is finished. To enable sweep mode within any region, program the appropriate SWEEP register to high. Figure 40 shows an example of the sweep mode operation. The number of vertical pulses needed depends on the vertical resolution of the CCD. The XV output signals are generated using the vertical pattern registers (shown in Table 15). A single pulse is created using the polarity and toggle position registers. The number of repetitions is then programmed to match the number of vertical shifts required by the CCD. Repetitions are programmed in the vertical sequence registers using the VPATREP registers. This produces a pulse train of the appropriate length. Normally, the pulse train is truncated at the end of the HD line length, but with sweep mode enabled for this region, the HD boundaries are ignored. In Figure 40, the sweep region occupies 23 HD lines. After the sweep mode region is completed in the next region, normal sequence operation will resume. When using sweep mode, be sure to set the region boundaries to the appropriate lines (using the sequence change positions) to prevent the sweep operation from overlapping the next vertical sequence.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region may be configured into a multiplier region. This mode uses the vertical pattern registers in a slightly different manner. Multiplier mode can be used to support unusual CCD timing requirements, such as vertical pulses that are wider than a single HD line length. The start polarity and toggle positions are still used in the same manner as the standard VPAT group programming, but the VPATLEN is used differently. Instead of using the pixel counter (HD counter) to specify the toggle position locations (VTOG1, 2, 3) of the VPAT group, the VPATLEN is multiplied with the VTOG position to allow very long pulses to be generated. To calculate the exact toggle position, counted in pixels after the start position, use the following equation:
Multiplier Mode Toggle Position = VTOG x VPATLEN
Because the VTOG register is multiplied by VPATLEN, the resolution of the toggle position placement is reduced. If VPATLEN = 4, then the toggle position accuracy will be reduced to a 4-pixel step size, instead of a single pixel step size. Table 16 summarizes how the VPAT group registers are used in multiplier mode operation. In multiplier mode, the VPATREPO and VPATREPE registers should always be programmed to the same value as the highest toggle position. The example shown in Figure 41 illustrates this operation. The first toggle position is two, and the second toggle position is nine. In nonmultiplier mode, this would cause the vertical sequence to toggle at pixel 2 and then pixel 9 within a single HD line. However, now toggle positions are multiplied by the VTPLEN = 4, so the first toggle occurs at pixel count = 8, and the second toggle occurs at pixel count = 36. Sweep mode has also been enabled to allow the toggle positions to cross the HD line boundaries.
Table 16. Multiplier MODE Register Parameters
Register MULTI XVPOL XVTOG1 XVTOG2 XVTOG3 VPATLEN VPATREP Length 1b 1b 12 b 12 b 12 b 10 b 12 b Range High/Low High/Low 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 1023 Pixels 0 to 4095 Description High Enables Multiplier Mode. Starting Polarity of XV Signal in Each VPAT Group. First Toggle Position for XV Signal in Each VPAT Group. Second Toggle Position for XV Signal in Each VPAT Group. Third Toggle Position for XV Signal in Each VPAT Group. Used as Multiplier Factor for Toggle Position Counter. VPATREPE/VPATREPO Should Be Set to the Same Value as TOG2 or TOG3.
Rev. A | Page 31 of 96
AD9925
VD SCP 1 SCP 2
HD
LINE 0
LINE 1
LINE 2
LINE 24
LINE 25
XV1 TO XV8
04637-0-033
REGION 0
REGION 1: SWEEP REGION
REGION 2
Figure 40. Example of Sweep Region for High Speed Vertical Shift
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE VERTICAL SEQUENCE REGISTERS
HD 3 VPATLEN 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 5 5
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
PIXEL NUMBER
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4 XV1 TO XV8 1 2 2
4
MULTIPLIER MODE VERTICAL PATTERN GROUP PROPERTIES: 1. START POLARITY (ABOVE: STARTPOL = 0). 2. FIRST, SECOND, AND THIRD TOGGLE POSITIONS (ABOVE: VTOG1 = 2, VTOG2 = 9). 3. LENGTH OF VPAT COUNTER (ABOVE: VPATLEN = 4); THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES. 4. TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTOG x VPATLEN). 5. IF SWEEP REGION IS ENABLED, THE VERTICAL PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE.
Figure 41. Example of Multiplier Region for Wide Vertical Pulse Timing
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the sensor gates (SG) are used to transfer the pixel charges from the light-sensitive image area into the light-shielded vertical registers. From the light-shielded vertical registers, the image is then clocked out line-by-line, using the vertical transfer pulses in conjunction with the high speed horizontal clocks. Table 17 contains the summary of the SG pattern registers. The AD9925 has six SG outputs, XSG1 to XSG6. Each of the outputs can be assigned to one of four programmed patterns by using the SGPATSEL registers. Each pattern is generated in a similar manner as the vertical pattern groups, with a programmable start polarity (SGPOL), first toggle position (SGTOG1), and second toggle position (SGTOG2). The active line where the SG pulses occur is programmable using the SGLINE1 and
SGLINE2 registers. Additionally, any of the XSG1 to XSG6 outputs may be individually disabled by using the SGMASK register. The individual masking allows all of the SG patterns to be preprogrammed, and the appropriate pulses for the different fields can be separately enabled. For maximum flexibility, the SGPATSEL, SGMASK, and SGLINE registers are separately programmable for each field. See the Complete Field: Combining Vertical Sequences section for more details. Additionally, there is a register in Bank 1 (Addr 0x55) that overrides the SG masking in the field registers (Bank 2). The SGMASK_OVR register allows sensor gate masking to be changed without modifying the field register values. Setting the SGMASKOVR_EN bit high enables the SGMASK override function. The SGMASK_OVR register is SCK updated, so the new SG masking values will update immediately.
Rev. A | Page 32 of 96
04637-0-034
AD9925
Table 17. SG Pattern Registers (Also See Field Registers in Table 15)
Register SGPOL SGTOG1 SGTOG2 SGMASK_OVR SGMASKOVR_EN Length 1b 12 b 12 b 6b 1b Range High/Low 0 to 4095 Pixel Location 0 to 4095 Pixel Location Six Individual Bits Disable/Enable Description Sensor Gate Starting Polarity for SG Pattern 0 to 3 First Toggle Position for SG Pattern 0 to 3 Second Toggle Position for SG Pattern 0 to 3 SG Masking, Overrides the Values in the Field Registers 1: Enables SGMASK Fast Update
VD 4
HD
1 XSG PATTERNS
2
Figure 42. Vertical Sensor Gate Pulse Placement
MODE Register
The MODE register is a single register that selects the field timing of the AD9925. Typically, all the field, vertical sequence, and vertical pattern group information is programmed into the AD9925 at startup. During operation, the MODE register allows the user to select any combination of field timing to meet the current requirements of the system. The advantage of using the MODE register in conjunction with preprogrammed timing is that it greatly reduces the system programming requirements during camera operation. Only a few register writes are required when the camera operating mode is changed, rather than having to write in all the vertical timing information with each camera mode change. A basic still camera application might require five different fields of vertical timing: one for draft mode operation, one for autofocusing, and three for still image readout. All of the register timing information for the five fields would be loaded at startup. Then, during camera operation, the MODE register would select Table 18. MODE Register Data Bit Breakdown (D23 = MSB)
D23 D22 D21 Total Number of Fields to Use 1 = First Field Only 7 = All 7 Fields 0 = Invalid D20 D19 D18 Seventh Field 0 = Field 0 5 = Field 5 6, 7 = Invalid D17 D16 D15 Sixth Field 0 = Field 0 5 = Field 5 6, 7 = Invalid D14 D13 D12 Fifth Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
which field timing would be active depending on how the camera was being used. Table 18 shows how the MODE register data bits are used. The three MSBs, D23 to D21, are used to specify how many total fields will be used. Any value from 1 to 7 can be selected using these three bits. The remaining register bits are divided into 3-bit sections to select which of the six fields are used and in which order. Up to seven fields may be used in a single MODE write. The AD9925 will start with the field timing specified by the first field bits, and on the next VD it will switch to the timing specified by the second field bits, and so on. After completing the total number of fields specified in Bits D23 to D21, the AD9925 will repeat by starting at the first field again. This will continue until a new write to the MODE register occurs. Figure 43 shows examples of the MODE register settings for different field configurations.
D11 D10 D9 Fourth Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
D8 D7 D6 Third Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
D5 D4 D3 Second Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
D2 D1 D0 First Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
Rev. A | Page 33 of 96
04637-0-035
3 PROGRAMMABLE SETTINGS FOR EACH PATTERN: 1. START POLARITY OF PULSE. 2. FIRST TOGGLE POSITION. 3. SECOND TOGGLE POSITION. 4. ACTIVE LINE FOR XSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN).
AD9925
EXAMPLE 1: TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2 MODE REGISTER CONTENTS = 0x60 0088 FIELD 0 FIELD 1 FIELD 2
EXAMPLE 2: TOTAL FIELDS = 2, FIRST FIELD = FIELD 3, SECOND FIELD = FIELD 4 MODE REGISTER CONTENTS = 0x40 0023 FIELD 3 FIELD 4
EXAMPLE 3: TOTAL FIELDS = 4, FIRST FIELD = FIELD 5, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 4, FOURTH FIELD = FIELD 2 MODE REGISTER CONTENTS = 0x80 050D FIELD 5 FIELD 1 FIELD 4 FIELD 2
04637-0-036
Figure 43. Using the MODE Register to Select Field Timing
VERTICAL TIMING EXAMPLE
To better understand how the AD9925 vertical timing generation is used, consider CCD timing chart in Figure 44. This particular example illustrates a CCD using a general 3-field readout technique. As described in the previous field section, each readout field should be divided into separate regions to perform each step of the readout. The sequence change positions (SCP) determine the line boundaries for each region, and then the VSEQSEL registers assign a particular vertical sequence to each region. The vertical sequences contain the specific timing information required in each region: XV1 to XV6 pulses (using VPAT groups), HBLK/CLPOB timing, and XSG patterns for the SG active lines. This particular timing example requires four regions for each of the three fields, labeled Region 0, Region 1, Region 2, and Region 3. Because the AD9925 allows up to six individual fields to be programmed, the Field 0, Field 1, and Field 2 registers can be used to meet the requirements of this timing example. The four regions for each field are very similar in this example, but the individual registers for each field allow flexibility to accommodate other timing charts. Region 0 is a high speed vertical shift region. Sweep mode may be used to generate this timing operation, with the desired
number of high speed vertical pulses needed to clear any charge from the CCD's vertical registers. Region 1 consists of only two lines and, like Region 3, uses standard single line vertical shift timing. Region 2 is the sensor gate line, where the VSG pulses transfer the image into the vertical CCD registers. This region may require the use of the second vertical pattern group for the SG active line. In summary, four regions are required in each of the three fields. The timing for Region 1 and Region 3 is essentially the same, reducing the complexity of the register programming. However, other registers will need to be used during the actual readout operation, such as the MODE register, shutter control registers (TRIGGER, SUBCK, VSUB, MSHUT, and STROBE), and the AFE gain register. These registers will be explained in other examples.
Important Note about Signal Polarities
When programming the AD9925 to generate the XV1 to XV8, XSG1 to XSG6, and SUBCK signals, it is important to note that the vertical driver circuit will invert these signals. Carefully check the required timing signals needed at the output of the vertical driver circuit and adjust the polarities of the XV signals accordingly.
Rev. A | Page 34 of 96
EXPOSURE (tEXP) FIRST FIELD READOUT THIRD FIELD READOUT SECOND FIELD READOUT
VD
HD
V1
V2
V3
V4
V5
V6
2 5 8 11 14 17 20
N-4 N-1
Figure 44. CCD Timing Example--Dividing Each Field into Regions
REGION 0 REGION 1 FIELD 0 REGION 2
REGION 3
N-5 N-2
REGION 0 REGION 1
REGION 3 REGION 2 FIELD 1
REGION 0 REGION 1
REGION 3 REGION 2 FIELD 2
04637-0-037
N-3 N
CCD OUT
1 4 7 10 13 16
3 6 9 12 15 18 21
Rev. A | Page 35 of 96
SUBCK
MSHUT OPEN
OPEN
CLOSED
VSUB
AD9925
AD9925
SHUTTER TIMING CONTROL
The CCD image exposure time is controlled by the substrate clock signal (SUBCK), which pulses the CCD substrate to clear out accumulated charge. The AD9925 supports three types of electronic shuttering: normal, high precision, and low speed. Along with the SUBCK pulse placement, the AD9925 can accommodate different readout configurations to further suppress the SUBCK pulses during multiple field readouts. The AD9925 also provides programmable outputs to control an external mechanical shutter (MSHUT), a strobe/flash (STROBE), and the CCD bias select signal (VSUB).
High Precision Shutter Operation
High precision shuttering is used in the same manner as normal shuttering, but it uses an additional register to control the last SUBCK pulse. In this mode, the SUBCK still pulses once per line, but the last SUBCK in the field will have an additional SUBCK pulse, the location of which is determined by the SUBCK2TOG register, as shown in Figure 46. Finer resolution of the exposure time is possible using this mode. Leaving the SUBCK2TOG register set to its maximum value (0xFF FFFF) will disable the last SUBCK pulse (default setting).
Low Speed Shutter Operation
Normal and high precision shutter operations are used when the exposure time is less than one field long. For exposure times longer than one field interval, low speed shutter operation is used. The AD9925 uses a separate exposure counter to achieve long exposure times. The number of fields for the low speed shutter operation is specified in the EXPOSURE register (Addr 0x62). As shown in Figure 47, this shutter mode will suppress the SUBCK and VSG outputs for up to 4095 fields (VD periods). The VD and HD outputs may be suppressed during the exposure period by programming the VDHDOFF register to 1. To generate a low speed shutter operation, it is necessary to trigger the start of the long exposure by writing to the TRIGGER Register Bit D3. When this bit is set high, at the next VD edge, the AD9925 will begin an exposure operation. If a value greater than 0 is specified in the EXPOSURE register, AD9925 will suppress the SUBCK output on subsequent fields. If the exposure is generated using the TRIGGER register and the EXPOSURE register is set to 0, then the behavior of the SUBCK will not be any different than that of normal shutter or high precision shutter operations, in which the TRIGGER register is not used.
Normal Shutter Operation
By default, the AD9925 always operates in the normal shutter configuration, in which the SUBCK signal pulses in every VD field (see Figure 45). The SUBCK pulse occurs once per line, and the total number of repetitions within the field will determine the length of the exposure time. The SUBCK pulse polarity and toggle positions within a line are programmable using the SUBCKPOL and SUBCK1TOG registers (see Table 19). The number of SUBCK pulses per field is programmed in the SUBCKNUM register (Addr 0x63). As shown in Figure 45, the SUBCK pulses will always begin in the line following the SG active line, which is specified in the SGACTLINE registers for each field. The SUBCKPOL, SUBCK1TOG, SUBCK2TOG, SUBCKNUM, and SUBCKSUPPRESS registers are updated at the start of the line after the sensor gate line, as described in the Updating New Register Values section.
VD
HD
XSG
tEXP
SUBCK
tEXP
SUBCK PROGRAMMABLE SETTINGS: 1. PULSE POLARITY USING THE SUBCKPOL REGISTER. 2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBNUM = 3 IN THE ABOVE EXAMPLE). 3. PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSE WIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTER.
Figure 45. Normal Shutter Mode
Rev. A | Page 36 of 96
04637-0-038
AD9925
VD
HD
XSG
tEXP
SUBCK NOTES 1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE. 2. LOCATION OF SECOND PULSE IS FULLY PROGRAMMABLE USING THE SUBCK2 TOGGLE POSITION REGISTER.
tEXP
Figure 46. High Precision Shutter Mode
TRIGGER EXPOSURE
VD
XSG
tEXP
SUBCK NOTES 1. SUBCK MAY BE SUPPRESSED FOR MULTIPLE FIELDS BY PROGRAMMING THE EXPOSURE REGISTER GREATER THAN ZERO. 2. ABOVE EXAMPLE USES EXPOSURE = 1. 3. TRIGGER REGISTER MUST ALSO BE USED TO START THE LOW SPEED EXPOSURE. 4. VD/HD OUTPUTS MAY ALSO BE SUPPRESSED USING THE VDHDOFF REGISTER = 1.
Figure 47. Low Speed Shutter Mode Using EXPOSURE Register
Table 19. Shutter MODE Register Parameters
Register TRIGGER READOUT EXPOSURE VDHDOFF SUBCKPOL1 SUBCK1TOG1 SUBCK2TOG1 SUBCKNUM1 SUBCKSUPPRESS1 Length 5b 3b 12 b 1b 1b 24 b 24 b 12 b 12 b Range On/Off for Five Signals 0 to 7 Number of Fields 0 to 4095 Number of Fields On/Off High/Low 0 to 4095 Pixel Locations 0 to 4095 Pixel Locations 1 to 4095 Number of Pulses 0 to 4095 Number of Pulses Description Trigger for VSUB [0], MSHUT [1], STROBE [2], Exposure [3], and Readout Start [4] Number of Fields to Suppress SUBCK after Exposure Number of Fields to Suppress to SUBCK and VSG during Exposure Time (Low Speed Shutter) Disable VD/HD Output during Exposure (1 = On, 0 = Off) SUBCK Start Polarity for SUBCK1 and SUBCK2 Toggle Positions for First SUBCK Pulse (Normal Shutter) Toggle Positions for Second SUBCK Pulse in Last Line (High Precision) Total Number of SUBCKs per Field, at 1 Pulse per Line Number of Lines to Further Suppress SUBCK after the VSG Line
1
Register is not VD updated, but is updated at the start of the line after the sensor gate line.
Rev. A | Page 37 of 96
04637-0-040
04637-0-039
AD9925
SUBCK Suppression
Normally, the SUBCKs will begin to pulse on the line following the sensor gate line (VSG). With some CCDs, the SUBCK pulse needs to be suppressed for one or more lines following the VSG line. The SUBCKSUPPRESS register allows for the suppression of the SUBCK pulses for lines following the VSG line. It is possible to independently trigger the readout operation without triggering the exposure operation. This will cause the readout to occur at the next VD, and the SUBCK output will be suppressed according to the value of the READOUT register. The TRIGGER register is also used to control the STROBE, MSHUT, and VSUB signal transitions. Each of these signals is individually controlled, although they will be dependent on the triggering of the exposure and readout operation. See Figure 49 for a complete example of triggering the exposure and readout operations.
Readout after Exposure
After the exposure, the readout of the CCD data occurs, beginning with the sensor gate (VSG) operation. By default, the AD9925 is generating the VSG pulses in every field. In the case where only a single exposure and a single readout frame is needed, such as the CCD's preview mode, the VSG and SUBCK pulses can operate in every field. However, in many cases, during readout, the SUBCK output needs to be further suppressed until the readout is completed. The READOUT register specifies the number of additional fields after the exposure to continue the suppression of SUBCK. READOUT can be programmed for zero to seven additional fields and should be preprogrammed at startup, not at the same time as the exposure write. A typical interlaced CCD frame readout mode will generally require two additional fields of SUBCK suppression (READOUT = 2). A 3-field, 6-phase CCD will require three additional fields of SUBCK suppression after the readout begins (READOUT = 3). If the SUBCK output is required to start back up during the last field of readout, simply program the READOUT register to one less than the total number of CCD readout fields. Like the exposure operation, the readout operation must be triggered using the TRIGGER register.
VSUB Control
The CCD readout bias (VSUB) can be programmed to accommodate different CCDs. Figure 48 shows two different modes that are available. In Mode 0, VSUB goes active during the field of the last SUBCK when the exposure begins. The on position (rising edge in Figure 48) is programmable to any line within the field. VSUB will remain active until the end of the image readout. In Mode 1, the VSUB is not activated until the start of the readout. An additional function called VSUB keep-on is also available. When this bit is set high, the VSUB output will remain on (active) even after the readout has finished. To disable the VSUB, set this bit back to low.
MSHUT and STROBE Control
MSHUT and STROBE operation is shown in Figure 49, Figure 50, and Figure 51. Table 20 shows the registers parameters for controlling the MSHUT and STROBE outputs. The MSHUT output is switched on with the MSHUTON registers, and it will remain on until the location specified in the MSHUTOFF is reached. The location of MSHUTOFF is fully programmable to anywhere within the exposure period, using the FD (field), LN (line), and PX (pixel) registers. The STROBE pulse is defined by the on and off positions. STROBON_FD is the field in which the STROBE is turned on, measured from the field containing the last SUBCK before exposure begins. The STROBON_ LN PX register gives the line and pixel positions with respect to STROBON_FD. The STROBE off position is programmable to any field, line, and pixel location with respect to the field of the last SUBCK.
Using the TRIGGER Register
As described above, by default, the AD9925 will output the SUBCK and VSG signals on every field. This works well for continuous single-field exposure and readout operations, such as the CCD's live preview mode. However, if the CCD requires a longer exposure time, or if multiple readout fields are needed, the TRIGGER register needs to initiate specific exposure and readout sequences. Typically, the exposure and readout bits in the TRIGGER register are used together. This will initiate a complete exposure-plus readout operation. Once the exposure has been completed, the readout will automatically occur. The values in the EXPOSURE and READOUT registers will determine the length of each operation.
Rev. A | Page 38 of 96
AD9925
TRIGGER VSUB
VD
XSG
tEXP
SUBCK 2 VSUB 1 MODE 0 2 MODE 1
READOUT
4 3
VSUB OPERATION: 1. ACTIVE POLARITY IS POLARITY (ABOVE EXAMPLE IS VSUB ACTIVE HIGH). 2. ON-POSITION IS PROGRAMMABLE, MODE 0 TURNS ON AT THE START OF EXPOSURE, MODE 1 TURNS ON AT THE START OF READOUT. 3. OFF-POSITION OCCURS AT END OF READOUT. 4. OPTIONAL VSUB KEEP-ON MODE WILL LEAVE THE VSUB ACTIVE AT THE END OF READOUT.
Figure 48. VSUB Programmability
TRIGGER EXPOSURE AND MSHUT
VD
XSG
tEXP
SUBCK
MSHUT 1
2
3 MSHUT PROGRAMMABLE SETTINGS: 1. ACTIVE POLARITY. 2. ON-POSITION IS VD UPDATED AND MAY BE SWITCHED ON AT ANY TIME. 3. OFF-POSITION CAN BE PROGRAMMED ANYWHERE FROM THE FIELD OF LAST SUBCK UNTIL THE FIELD BEFORE READOUT.
Figure 49. MSHUT Output Programmability
TRIGGER Register Limitations
Although the TRIGGER register can be used to perform a complete exposure and readout operation, there are limitations on its use. Once an exposure-plus readout operation has been triggered, another exposure/readout operation cannot be triggered right away. There must be at least one idle field (VD intervals) before the next exposure/readout can be triggered. The same limitation applies to the triggering of the MSHUT signal. There must be at least one idle field after the completion of the MSHUT OFF operation before another MSHUT OFF operation can be programmed.
The VSUB trigger requires two idle fields between exposure/readout operations in order to ensure proper VSUB on/off triggering. If the VSUB signal is not required to be turned on and off in between each successive exposure/readout operation, then this limitation can be ignored. Using the VSUB keep-on mode is useful when successive exposure/readout operations are required.
Rev. A | Page 39 of 96
04637-0-042
04637-0-041
AD9925
TRIGGER EXPOSURE AND STROBE
VD
XSG
tEXP
SUBCK
STROBE 1 2 3 STROBE PROGRAMMABLE SETTINGS: 1. ACTIVE POLARITY. 2. ON-POSITION IS PROGRAMMABLE IN ANY FIELD DURING THE EXPOSURE TIME (WITH RESPECT TO THE FIELD CONTAINING THE LAST SUBCK). 3. OFF-POSITION IS PROGRAMMABLE IN ANY FIELD DURING THE EXPOSURE TIME.
04637-0-043
Figure 50. STROBE Output Programmability
Table 20. VSUB, MSHUT, and STROBE Register Parameters
Register VSUBMODE[0] VSUBMODE[1] VSUBON[11:0] VSUBON[12] MSHUTPOL[0] MSHUTPOL[1] MSHUTON MSHUTOFF_FD MSHUTOFF_LNPX STROBPOL STROBON_FD STROBON_LNPX STROBOFF_FD STROBOFF_LNPX Length 1b 1b 12 b 1b 1b 1b 24 b 12 b 24 b 1b 12 b 24 b 12 b 24 b Range High/Low High/Low 0 to 4095 Line Location High/Low High/Low On/Off 0 to 4095 Line/Pixel Location 0 to 4095 Field Location 0 to 4095 Line/Pixel Location High/Low 0 to 4095 Field Location 0 to 4095 Line/Pixel Location 0 to 4095 Field Location 0 to 4095 Line/Pixel Location Description VSUB Mode (0 = Mode 0, 1 = Mode 1) (See Figure 44). VSUB Keep-On Mode. VSUB will stay active after readout when set high. VSUB On Position. Active starting in any line of field. VSUB Active Polarity. MSHUT Active Polarity. MSHUT Manual Enable (1 = Active or Open). MSHUT On Position Line [11:0] and Pixel [23:12] Location. Field Location to Switch Off MSHUT (Inactive or Closed). Line/Pixel Position to Switch Off MSHUT (Inactive or Closed). STROBE Active Polarity. STROBE ON Field Location, with Respect to Last SUBCK Field. STROBE ON Line/Pixel Position. STROBE OFF Field Location, with Respect to Last SUBCK Field. STROBE OFF Line/Pixel Position.
Rev. A | Page 40 of 96
SERIAL WRITES 9 2 6 7 8 10
1
VD STILL IMAGE READOUT
XSG 10
SUBCK 4
tEXP
STROBE 5 10
EXAMPLE OF EXPOSURE AND READOUT OF INTERLACED FRAME
Figure 51. Example of Exposure and Still Image Readout Using Shutter Signals and MODE Register
Rev. A | Page 41 of 96
OPEN CLOSED 3 MODE 0 MODE 1 STILL IMAGE FIRST FIELD DRAFT IMAGE
MSHUT
MECHANICAL SHUTTER
OPEN 10
VSUB
STILL IMAGE SECOND FIELD STILL IMAGE THIRD FIELD DRAFT IMAGE
CCD OUT
DRAFT IMAGE
04637-0-044
AD9925
AD9925
Refer to Figure 51 for each step: 1. Write to the READOUT register (Addr x61) to specify the number of fields to further suppress SUBCK while the CCD data is readout. In this example, READOUT = 3. Write to the EXPOSURE register (Addr x62) to specify the number of fields to suppress SUBCK and VSG outputs during exposure. In this example, EXPOSURE = 1. Write to the TRIGGER register (Addr x60) to enable the STROBE, MSHUT, and VSUB signals and to start the exposure/readout operation. To trigger these events (as in Figure 56), set the register TRIGGER = 31. Readout will automatically occur after the exposure period is finished. Write to the MODE register (x1B) to configure the next five fields. The first two fields during exposure are the same as the current draft mode fields, and the following three fields are the still frame readout fields. The registers for the draft mode field and the three readout fields have already been programmed. 2. 3. The VD/HD falling edge will update the serial writes from 1. If VSUB mode = 0 (Addr x67), VSUB output will turn on at the line specified in the VSUBON register (Addr x68). 4. STROBE output turns on and off at the location specified in the STROBEON and STROBEOFF registers (Addr x6E to x71). MSHUT output turns off at the location specified in the MSHUTOFF registers (Addr x6B and x6C). The next VD falling edge will automatically start the first readout field. The next VD falling edge will automatically start the second readout field. The next VD falling edge will automatically start the third readout field. Write to the MODE register to reconfigure the single draft mode field timing. Write to the MSHUTON register (Addr x6A) to open the mechanical shutter.
5. 6. 7. 8. 9.
10. VD/HD falling edge will update the serial writes from 9. VSG outputs return to draft mode timing. SUBCK output resumes operation. MSHUT output returns to the on position (active or open). VSUB output returns to the off position (inactive).
Rev. A | Page 42 of 96
AD9925
FG_TRIG OPERATION
The AD9925 contains an additional signal that may be used in conjunction with shutter operation or general system operation. The FG_TRIG signal is an internally generated pulse that can be output on the VSUB or SYNC pins for system use or combined with the VSUB registers to create a four-toggle VSUB signal. The FG_TRIG signal is generated using the start polarity and first and second toggle position registers, programmable with line and pixel resolution. The field placement of the FG_TRIG pulse is matched to the field count specified by the MODE register operation. The FG_TRIGEN register contains a 3-bit value to specify which field count will contain the FG_TRIG pulse. Figure 53 shows how the FG_TRIG pulse is generated using these registers. After the FG_TRIG signal is specified, it is enabled using Bit 3 of the FG_TRIGEN register. By default, the FG_TRIG will be mapped to the SYNC output, as long as the SYNC pin is configured as an output (SYNCENABLE = 1). Alternatively, the FG_TRIG pulse may be mapped to the VSUB output by writing a 1 to the SHUT_EXTRA Register Bit 3. One final application for the FG_TRIG signal is to combine it with the existing VSUB signal to generate additional toggle positions. By setting the SHUT_EXTRA Bit 8 to a 1, the VSUB toggles and FG_TRIG toggles are XOR'd together and sent to the VSUB output. Figure 52 and Figure 54 show this application in more detail.
FG_TRIG INTERNAL XOR VSUB INTERNAL 1 2:1 0
1 2:1 0 VSUB OUTPUT
SHUT_EXTRA[3] SHUT_EXTRA[8]
Figure 52. Combining the Internal FG_TRIG and Internal VSUB Signals
Table 21. FG_TRIG Operation Registers
Register SYNCENABLE VSUBON SHUT_EXTRA Address 0x12 0x68 0xE7 Bit Width [0] [12:0] [8:0] Description 1: Configures SYNC Pin as an Output. By default, the FG_TRIG signal outputs on the SYNC pin. Controls VSUB On Position and Polarity. When SHUT_Extra [8] = 1, FG_TRIG toggles are combined with VSUB signal. Selects Whether FG_TRIG Signal Is Used with VSUB. [2:0] Set to 0. [3] Set = 1 to send FG_TRIG signal to VSUB pin. [7:4] Set to 0. [8] Set = 1 to combine FG_TRIG and VSUB signals. FG_TRIG Enable. [2:0] Selects field count for pulse (based on mode field counter). [3] Set = 1 to enable FG_TRIG signal output. FG_TRIG Start Polarity. FG_TRIG First Toggle Position, Line Location. FG_TRIG First Toggle Position, Pixel Location. FG_TRIG Second Toggle Position, Line Location. FG_TRIG Second Toggle Position, Pixel Location.
FG_TRIGEN
0xEB
[3:0]
FG_TRIGPOL FG_TRIGLINE1 FG_TRIGPIX1 FG_TRIGLINE2 FG_TRIGPIX2
0xF2 0xF3 0xF4 0xF5 0xF6
[0] [11:0] [12:0] [11:0] [12:0]
Rev. A | Page 43 of 96
04637-0-074
AD9925
VD
MODE REGISTER FIELD COUNT
FIELD 0 4
FIELD 1
FIELD 2 4
FIELD 0
FIELD 1
FG_TRIG
1 2 3 FG_TRIG PROGRAMMABLE SETTINGS: 1. ACTIVE POLARITY. 2. FIRST TOGGLE POSITION, LINE AND PIXEL LOCATION. 3. SECOND TOGGLE POSITION, LINE AND PIXEL LOCATION. 4. FIELD PLACEMENT BASED ON MODE REGISTER FIELD COUNT.
Figure 53. Generating the FG_TRIG Signal
VD
VSUB INTERNAL FG_TRIG INTERNAL VSUB OUT SHUT_XTRA[8] = 0 VSUB OUT SHUT_XTRA[8] = 1
04637-0-067
Figure 54. Combining FG_TRIG and VSUB to Create Four Toggle Positions for VSUB Output
Rev. A | Page 44 of 96
04637-0-066
AD9925
1.0F 1.0F REFB REFT DC RESTORE 1.3V SHP 1.0V 2.0V CLI INTERNAL VREF SHD FIXED DELAY 1 DCLK 0 DOUT DLY 6dB ~ 42dB VGA 2V FULL SCALE 12-BIT ADC OUTPUT DATA LATCH
DOUT PHASE
DCLK MODE 12 DOUT
0.1F
CCDIN CDS
OPTICAL BLACK CLAMP VGA GAIN REGISTER DAC CLPOB PBLK DIGITAL FILTER 8 SHP DOUT SHD PHASE CLPOB PBLK CLAMP LEVEL REGISTER
CLI
AD9925
Figure 55. Analog Front End Functional Block Diagram
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9925 signal processing chain is shown in Figure 55. Each processing step is essential in achieving a high quality image from the raw CCD pixel data.
Variable Gain Amplifier
The VGA stage provides a gain range of 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V fullscale systems, the equivalent gain range is 0 dB to 36 dB. The VGA gain curve follows a linear-in-dB characteristic. The exact VGA gain can be calculated for any gain register value by using the equation Gain (dB) = (0.0351 x Code) + 6 dB where the Code range is 0 to 1023.
42
DC Restore
To reduce the large dc offset of the CCD output signal, a dcrestore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.3 V, which allows it to be compatible with the 3 V supply voltage of the AD9925.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the video information and reject the low frequency noise. The timing shown in Figure 19 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference level and data level of the CCD signal, respectively. The placement of the SHP and SHD sampling edges is determined by setting the SAMPCONTROL register located at Addr 0x36. Placement of these two clock signals is critical in achieving the best performance from the CCD.
36
VGA GAIN (dB)
30
24
18
12
04637-A-002
PRECISION TIMING GENERATION
V-H TIMING GENERATION
6 0 127 255 383 511 639 767 VGA GAIN REGISTER CODE 895 1023
Figure 56. VGA Gain Curve
Rev. A | Page 45 of 96
04637-0-046
AD9925
ADC
The AD9925 uses high performance ADC architecture, optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB. The ADC uses a 2 V input range. See Figure 10, Figure 12, and Figure 13 for typical linearity and noise performance plots for the AD9925.
Digital Data Outputs
The AD9925 digital output data is latched using the DOUT PHASE register value, as shown in Figure 55. Output data timing is shown in Figure 21 and Figure 22. It is also possible to leave the output latches transparent, so that the data outputs are valid immediately from the ADC. Programming the AFE CONTROL Register Bit D4 to a 1 will set the output latches transparent. The data outputs can also be disabled (three stated) by setting the AFE CONTROL Register Bit D3 to a 1. The switching of the data outputs can couple noise back to the analog signal path. To minimize any switching noise, it is recommended that the DOUT PHASE register be set to the same edge as the SHP sampling location, or up to 12 edges after the SHP sampling location. Other settings can produce good results, but experimentation is necessary. It is recommended that the DOUT PHASE location not occur between the SHD sampling location and 12 edges after the SHD location. For example, if SHDLOC = 0, then DOUT PHASE should be set to an edge location of 12 or greater. If adjustable phase is not required for the data outputs, the output latch can be left transparent using register 0x03, Bit [4]. The data output coding is normally straight binary, but the coding may be changed to gray coding by setting the AFE CONTROL Register Bit D5 to a 1.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD's black level. During the optical black (shielded) pixel inter val on each line, the ADC output is compared with a fixed black level reference, selected by the user in the clamp level register. The value can be programmed between 0 LSB and 255 LSB in 256 steps. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a DAC. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the postprocessing, the AD9925 optical black clamping may be disabled using Bit D2 in the OPRMODE register. When the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. The CLPOB pulse should be placed during the CCD's optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide. Shorter pulse widths may be used, but the ability to track low frequency variations in the black level will be reduced. See the Horizontal Clamping and Blanking section for timing examples.
Rev. A | Page 46 of 96
AD9925
VERTICAL DRIVER SIGNAL CONFIGURATION
As shown in Figure 57, XV1 to XV8, XSG1 to XSG6, and XSUBCK are outputs from the internal AD9925 timing generator, while V1 to V8 and SUBCK are the resulting outputs from the AD9925 vertical driver. The vertical driver performs the mixing of the XV and XSG pulses and amplifies them to the high voltages required for driving the CCD. Additionally, the vertical driver outputs are inverted from the internal XV, XSG, and SUBCK polarities configured by the AD9925 registers. Table 22 to Table 32 describe the output polarities for these signals vs. their input levels. Refer to these tables when determining the register settings for the desired output levels. Figure 58 to Figure 64 show graphically the relationship between the polarities of the XV and XSG signals and the inverted vertical driver output signals.
AD9925
VERTICAL DRIVER +3V XV1 XSG1 XV2 XSG6 XSG2 XV3 C9 XSG3 INTERNAL TIMING GENERATOR XSG4 XV5 E9 XSG5 XV4 G10 V4 H10 V6 K10 V7 J9 2-LEVEL OUTPUTS V5B D9 V5A V3B B9 V3A 3-LEVEL OUTPUTS G11 V2 +15V, -7.5V B8 V1
XV6
XV7
XV8
V8
XSUBCK
J8
04637-0-047
SUBCK
Figure 57. AD9925 Internal V-Driver Input Signals
Rev. A | Page 47 of 96
AD9925
Table 22. V1 Output Polarity
XV1 L L H H V-Driver Input XSG1 L H L H V1 Output VH VM VL VL
Table 27. V5A Output Polarity
XV5 L L H H V-Driver Input XSG4 L H L H V5A Output VH VM VL VL
Table 23. V2 Output Polarity
XV2 L L H H V-Driver Input XSG6 L H L H V2 Output VH VM VL VL
Table 28. V5B Output Polarity
XV5 L L H H V-Driver Input XSG5 L H L H V5B Output VH VM VL VL
Table 24. V3A Output Polarity
XV3 L L H H V-Driver Input XSG2 L H L H V3A Output VH VM VL VL
Table 29. V6 Output Polarity
V-Driver Input XV6 L H V6 Output VM VL
Table 30. V7 Output Polarity
V-Driver Input XV7 L H V7 Output VM VL
Table 25. V3B Output Polarity
XV3 L L H H V-Driver Input XSG3 L H L H V3B Output VH VM VL VL
Table 31. V8 Output Polarity
V-Driver Input XV8 L H V8 Output VM VL
Table 26. V4 Output Polarity
V-Driver Input XV4 L H V4 Output VM VL
Table 32. SUBCK Output Polarity
V-Driver Input XSUBCK L H SUBCK Output VH VL
Rev. A | Page 48 of 96
AD9925
XV1
XSG1
VH VM VL
04637-0-048
V1
Figure 58. XV1, XSG1, and V1 Output Polarities
XV2
XSG6
VH VM VL
04637-0-049
V2
Figure 59. XV2, XSG6, and V2 Output Polarities
XV3
XSG2
VH
04637-0-050
V3A
VM VL
Figure 60. XV3, XSG2, and V3A Output Polarities
XV3
XSG3
VH
04637-0-051
V3B
VM VL
Figure 61. XV3, XSG3, and V3B Output Polarities
Rev. A | Page 49 of 96
AD9925
XV5
XSG4
VH
04637-0-052
V5A
VM VL
Figure 62. XV5, XSG4, and V5A Output Polarities
XV5
XSG5
VH
04637-0-053
V5B
VM VL
Figure 63. XV5, XSG5, and V5B Output Polarities
XV4, XV6, XV7, XV8
V4, V6, V7, V8
VM VL
Figure 64. XV4, XV6, XV7, XV8 and V4, V6, V7, V8 Output Polarities
Rev. A | Page 50 of 96
04637-0-054
AD9925
POWER-UP AND SYNCHRONIZATION
Vertical Driver Power Supply Sequencing
The recommended Power-Up and Power-Down sequences are shown in Figure 65 and Figure 66, respectively. As shown, the VM1 and VM2 voltage levels should never exceed the VH1 and VH2 voltage levels during power-up or power-down. Excessive current will result if this requirement is not met due to a PN junction diode turning on between the VM1/VM2 and VH supply pins.
VH1 = VH2 = 12.0V TO 15.0V
VDVDD = DVDD = DRVDD = HVDD = RGVDD = TCVDD = AVDD = 3.0V
1 0V
2 VM1 = VM2 = -1.0V TO -0.5V
SAME TIME AS VM AND VH; LATER OR EARLIER IS OK, BUT NOT BEFORE VDD REACHES 3.0V.
Figure 65. Power-Up Sequence
VH1 = VH2
VDVDD = DVDD = DRVDD = HVDD = RGVDD = TCVDD = AVDD = 3V
1 VM1 = VM2
2 0V
VL
04637-0-056
SAME TIME AS VM AND VH OR EARLIER, BUT NOT AFTER VDD.
Figure 66. Power-Down Sequence
Rev. A | Page 51 of 96
04637-0-055
VL = -7.5V
AD9925
VH1 = VH2 = 15.0V VDVDD = DVDD = DRVDD = HVDD = RGVDD = TCVDD = AVDD = 3V POWER SUPPLIES 0V 1 4 VL = -7.5V CLI (INPUT) 2 SERIAL WRITES 12 SYNC (INPUT) 3 5 6 7 8 9 10 11
tSYNC
1V 1ST FIELD 1H
VD (OUTPUT)
HD (OUTPUT) H2/H4 DIGITAL OUTPUTS H1/H3, RG, DCLK CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS UPDATED AT VD/HD EDGE
04637-0-069
Figure 67. Recommended Power-Up Sequence and Synchronization, Master Mode
Recommended Power-Up Sequence for Master Mode
When the AD9925 is powered up, the following sequence is recommended (refer to Figure 67 for each step). Note that a SYNC signal is required for master mode operation. If an external SYNC pulse is not available, it is also possible to generate an internal SYNC pulse by writing to the SYNCPOL register, as described in the next section. 1. 2. 3. Turn on power supplies for the AD9925 and apply master clock CLI. Reset the internal AD9925 registers by writing a 1 to the SW_RESET register (Addr 0x10 in Bank 1). Write to the standby mode polarity registers 0x0A to 0x0D to set the proper polarities for the V-driver inputs, in order to avoid damage to the CCD. See Table 35 for settings. The V-driver supplies, VH and VL, can then be powered up anytime after completing Step 3 to set the proper polarities. By default, the AD9925 is in standby 3 mode. To place the part into normal power operation, write 0x004 to the AFE OPRMODE register (Addr 0x00 in Bank 1). Write a 1 to the BANKSELECT register (Addr 0x7F)). This will select Register Bank 2. Load Bank 2 registers with the required VPAT group, vertical sequence, and field timing information.
7. 8.
Write a 0 to the BANKSELECT register to select Bank 1. By default, the internal timing core is held in a reset state with TGCORE_RSTB register = 0. Write a 1 to the TGCORE_RSTB register (Addr 0x15 in Bank 1) to start the internal timing core operation. Note: If a 2x clock is used for the CLI input, the CLIDIVIDE register (Addr 0x30) should be set to 1 before resetting the timing core. Load the required registers to configure the high speed timing, horizontal timing, and shutter timing information.
9.
10. Configure the AD9925 for master mode timing by writing a 1 to the MASTER register (Addr 0x20 in Bank 1). 11. Write a 1 to the OUT_CONTROL register (Addr 0x11 in Bank 1).This will allow the outputs to become active after the next SYNC rising edge. 12. Generate a SYNC event: If SYNC is high at power-up, bring the SYNC input low for a minimum of 100 ns. Then bring SYNC back to high. This will cause the internal counters to reset and will start the VD/HD operation. The first VD/HD edge allows most Bank 1 register updates to occur, including OUT_CONTROL to enable all outputs.
4. 5.
6.
Rev. A | Page 52 of 96
AD9925
Table 33. Power-Up Register Write Sequence
Address 0x10 0x0A to 0x0D 0x00 0x7F 0x00 to 0xFF 0x7F 0x15 0x31 to 0x71 0x20 0x11 0x13 Data 0x01 TBD 0x04 0x01 TBD 0x00 0x01 TBD 0x01 0x01 0x01 Description Reset All Registers to Default Values Standby V-Driver Input Signal Polarities Power-Up the AFE and CLO Oscillator Select Register Bank 2 VPAT, Vertical Sequence, and Field Timing Select Register Bank 1 Reset Internal Timing Core Horizontal and Shutter Timing Configure for Master Mode Enable All Outputs after SYNC SYNCPOL (for Software SYNC Only)
When the AD9925 is used in slave mode, the VD and HD inputs are used to synchronize the internal counters. Following a falling edge of VD, there will be a latency of 23 master clock edges (CLI) after the falling edge of HD until the internal H-Counter is reset. The reset operation is shown in Figure 69.
Vertical Toggle Position Placement near Counter Reset
One additional consideration during the reset of the internal counters is the vertical toggle position placement. Before the internal counters are reset, there is an area of 18 pixels where no toggle positions should be programmed. For master mode, the last 18 pixels before the HD falling edge should not be used for toggle position placement of the XV, XSG, SUBCK, HBLK, PBLK, or CLPOB pulses (see Figure 70). Figure 71 shows the same example for slave mode. The same restriction applies: the last 18 pixels before the counters are reset and cannot be used. However, in slave mode, the counter reset is delayed with respect to VD/HD placement; therefore, the inhibited area is different than it is in master mode.
Generating Software SYNC without External SYNC Signal
If an external SYNC pulse is not available, it is possible to generate an internal SYNC in the AD9925 by writing to the SYNCPOL register (Addr 0x13). If the software SYNC option is used, the SYNC input (Pin J5) should be tied to ground (VSS). After power-up, follow the same procedure as before, for Steps 1 through 11. Then, for Step 12, instead of using the external SYNC pulse, write a 1 to the SYNCPOL register. This will generate the SYNC internally, and the timing operation will begin.
Additional Considerations for Toggle Positions
In addition to avoiding toggle position placement near the counterreset location, there are a couple of other recommendations. Pixel location 0 should not be used for any of the toggle positions for the XSG and SUBCK pulses. Also, the propagation delay of the V-driver circuit should be considered when programming the toggle positions for the XV, XSG, and SUBCK pulses. The delay of the V-driver circuit is specified in Table 3 and is a maximum of 200 ns.
SYNC during Master Mode Operation
The SYNC input may be used any time during operation to resync the AD9925 counters with external timing, as shown in Figure 68. The operation of the digital outputs may be suspended during the SYNC operation by setting the SYNCSUSPEND register (Addr 0x14) to a 1.
Power-Up and Synchronization in Slave Mode
The power-up procedure for slave mode operation is the same as the procedure described for master mode operation, with two exceptions: 1. 2. Eliminate Step 10. Do not write the part into master mode. No SYNC pulse is required in slave mode. Substitute Step 12 with starting the external VD and HD signals. This will synchronize the part, allow the Bank 1 register updates, and start the timing operation.
Rev. A | Page 53 of 96
AD9925
SYNC
VD SUSPEND
HD
H124, RG, V1 TO 4, VSG, SUBCK NOTES 1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14). 4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H2, AND RG ARE HELD AT THEIR DEFAULT POLARITIES. 5. IF SYNCSUSPEND = 0, CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
Figure 68. SYNC Timing to Synchronize AD9925 with External Timing
VD
HD 3ns MIN CLI
H-COUNTER RESET
H-COUNTER (PIXEL COUNTER) X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
2
3
4
04637-0-076
NOTE INTERNAL H-COUNTER IS RESET 23 CLOCK EDGES AFTER THE HD FALLING EDGE.
Figure 69. External VD/HD and Internal H-Counter Synchronization, Slave Mode
VD H-COUNTER RESET HD NO TOGGLE POSITIONS ALLOWED IN THIS AREA H-COUNTER (PIXEL COUNTER)
N-22 N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 N-11 N-10 N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
0
1
2
3
4
04637-0-077
NOTE TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 18 PIXELS OF PIXEL 0 LOCATION.
Figure 70. Toggle Position Inhibit Area, Master Mode
VD
HD
H-COUNTER RESET NO TOGGLE POSITIONS ALLOWED IN THIS AREA
H-COUNTER (PIXEL COUNTER)
N-22 N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 N-11 N-10
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
0
1
2
3
4
04637-0-078
NOTE TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 18 PIXELS OF PIXEL 0 LOCATION.
Figure 71. Toggle Position Inhibit Area, Slave Mode
Rev. A | Page 54 of 96
04637-0-058
AD9925
STANDBY MODE OPERATION
The AD9925 contains three different standby modes to optimize the overall power dissipation in a particular application. Bits [1:0] of the OPRMODE register control the power-down state of the device: OPRMODE[1:0] = 00 = Normal Operation (Full Power) OPRMODE[1:0] = 01 = Standby 1 Mode OPRMODE[1:0] = 10 = Standby 2 Mode OPRMODE[1:0] = 11 = Standby 3 Mode (Lowest Overall Power) Table 34 and Table 35 summarize the operation of each powerdown mode. Note that the OUT_CONTROL register takes priority over the standby 1 and standby 2 modes in determining the digital output states, but the standby 3 mode takes priority over OUT_CONTROL. Standby 3 mode has the lowest power consumption and even shuts down the crystal oscillator circuit between CLI and CLO. Thus, if CLI and CLO are being used with a crystal to generate the master clock, this circuit will be powered down and there will be no clock signal. When returning from standby 3 mode to normal operation, the timing core must be reset at least 500 s after the OPRMODE register is written to. This will allow sufficient time for the crystal circuit to settle. The XV and shutter outputs can also be programmed to hold a specific value during any of the standby modes, as detailed in Table 35.
Table 34. Standby Mode Operation
I/O Block AFE Timing Core CLO Oscillator CLO H1 H2 H3 H4 RG VD HD DCLK DOUT Standby 3 (Default)1, 2 Off Off Off High Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Low Low Low Low OUT_CONT= LO2 No Change No Change No Change Running Low High Low High Low VDHDPOL Value VDHDPOL Value Low Low Standby 23, 4 Off Off On Running Low (4.3 mA) High (4.3 mA) Low (4.3 mA) High (4.3 mA) Low (4.3 mA) VDHDPOL Value VDHDPOL Value Low Low Standby 13, 4 Off Off On Running Low (4.3 mA) High (4.3 mA) Low (4.3 mA) High (4.3 mA) Low (4.3 mA) Undefined in Master Mode Undefined in Master Mode Running if DCLK MODE =1 Low
1 2
To exit standby 3 mode, first write a 00 to OPRMODE[1:0], then reset the timing core after ~500 s to guarantee proper settling of the oscillator. Standby 3 mode takes priority over OUT_CONTROL for determining the output polarities. 3 These polarities assume OUT_CONT = High., because OUT_CONTROL = Low takes priority over standby 1 and standby 2 modes. 4 Standby 1 and standby 2 modes will set H and RG drive strength to minimum value (4.3 mA).
Rev. A | Page 55 of 96
AD9925
Table 35. Standby Mode Operation--Vertical and Shutter Outputs (Programmable Polarities Available)
I/O Block XV1 XV8 XV3 XV7 XV6 XSG6 XV5 XV4 XSG5 XSG4 XV2 XSG3 XSG1 XSG2 SUBCK VSUB MSHUT STROBE Standby 3 (Default)1, 2 Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low OUT_CONT = Low2, 3 Low Low Low Low High High High High High High High High High High High Low Low Low Standby 23 Low Low Low Low High High High High High High High High High High High Low Low Low Standby 13 Low Low Low Low High High High High High High High High High High High Low Low Low
1 2
Polarities for vertical and shutter outputs are programmable for each standby mode, using the STBYPOL registers. Default register values are: STBY3POL = Bin 00000000000000000 = 0x00 OCONTPOL = STBY2POL = STBY1POL = Bin 000011111111111000 = 0x3FF8 3 Bit assignments for programming polarity registers: (MSB) XV1, XV8, XV3, XV7, XV6, XSG6, XV5, XV4, XSG5, XSG4, XV2, XSG3, XSG1, XSG2, SUBCK, VSUB, MSHUT, and STROBE (LSB).
Rev. A | Page 56 of 96
AD9925
CIRCUIT LAYOUT INFORMATION
The AD9925 typical circuit connections are shown in Figure 73. The PCB layout is critical in achieving good image quality from the AD9925. All of the supply pins, particularly the AVDD, TCVDD, RGVDD, and HVDD supplies, must be decoupled to ground with good quality, high frequency chip capacitors. The decoupling capacitors should be located as close as possible to the supply pins and should have a very low impedance path to a continuous ground plane. There should also be a 4.7 F or larger value bypass capacitor near each main supply--AVDD, HVDD, DRVDD, VL, and VH--although this is not necessary for each individual pin. In most applications, it is easier to share the supply for RGVDD and HVDD, which may be done as long as the individual supply pins are separately bypassed. A separate 3 V supply may also be used for DRVDD, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended. The analog bypass pins (REFT and REFB) should also be carefully decoupled to ground as close as possible to their respective pins. The analog input (CCDIN) capacitor should also be located close to the pin. The H1 to H4 and RG traces should be designed to have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand on H1 to H4 by the CCD. If possible, physically locating the AD9925 closer to the CCD will reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9925 to the CCD. The AD9925 also contains an on-chip oscillator for driving an external crystal. Figure 72 shows an example of an application using a typical 24 MHz crystal. For the exact values of the external resistors and capacitors, it is best to consult with the crystal manufacturer's data sheet.
AD9925
J6 CLI 1M J4 CLO 500 20pF
04637-0-060
20pF
24MHz XTAL
Figure 72. Crystal Driver Application
Rev. A | Page 57 of 96
AD9925
HORIZONTAL SYNC TO/FROM ASIC/DSP +3V ANALOG SUPPLY 0.1F -7.5V SUPPLY 3 +15V SUPPLY 0.1F 0.1F
VM2 STROBE
VERTICAL SYNC TO/FROM ASIC/DSP 10 VERTICAL CLOCK OUTPUTS (TO CCD) TO STROBE CIRCUIT SERIAL INTERFACE (FROM ASIC/DSP)
DVDD
DVSS HD
SDI
SCK
VM1
V3A
V3B V5A
V5B
NC VL VH1
NC
NC
VD V2
V1
V4 V6
V8
V7
DCLK TO ASIC/DSP
DCLK D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
E10 D11 C10 C11 B10 B11 A10 A9 A8 B7 A7 B6 A6 C5 B5 A5 A4 B4 C4 B3 A3 B2 A2 A1
K11 L11 L10 K9 K8 J8 J7 L9 L8 K7
SL NC RSTB VH2 VL SUBCK MSHUT REFB REFT AVDD CCDIN AVSS AVSS CLI TCVSS TCVSS SYNC CLO TCVDD TCVDD RGVDD RG RGVSS RGVSS 0.1F 1F 1F 0.1F 0.1F 0.1F 0.1F
EXTERNAL RESET INPUT (NORMALLY HIGH, PULSE LOW TO RESET) +15V SUPPLY -7.5V SUPPLY
G11
A11
F11 F10
E11 C6
G10
J9 H11
D10
H10
K10
J10
J11
G9
C7
C8
B8
B9
C9
D9
E9
F9
H9
SUBCK OUTPUT TO CCD TO SHUTTER CIRCUIT +3V ANALOG SUPPLY + 4.7F ANALOG OUTPUT FROM CCD
AD9925
NOT DRAWN TO SCALE
L6 L7 K6 J6 L5 K5 J5 J4 K4 K3 L4 L3 L2 K2
DATA OUTPUTS +3V DRIVER
12
D11 (MSB) DRVDD DRVSS VSUB 0.1F 0.1F VDVDD VDVSS NC NC NC NC NC NC
+ 4.7F
MASTER CLOCK INPUT EXTERNAL SYNC INPUT +3V ANALOG SUPPLY +3V H, RG SUPPLY 0.1F
VSUB TO CCD
G2
G3
G1
B1
C1
C2
C3
D1
D2
D3
E2
E3 E1
H1 H2
H3
K1
F2
F3
F1
HVSS HVSS
HVSS
NC NC
NC NC
NC
NC NC
NC
NC
HVSS
HVSS
H1
HVDD HVDD
H3 H4
H2 HVDD
HVDD
HVDD
NC
L1
J2
J3
J1
3
H1 TO H4, RG OUTPUTS (TO CCD)
04637-0-061
0.1F
+
+3V H, RG SUPPLY 4.7F
Figure 73. AD9925 Typical Circuit Configuration
Rev. A | Page 58 of 96
AD9925
SERIAL INTERFACE TIMING
All of the internal registers of the AD9925 are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit dataword are written starting with the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 74. Although many registers are fewer than 24 bits wide, all 24 bits must be written for each register. For example, if the register is only 10 bits wide, then the upper 14 bits are Don't Cares and may be filled with 0s during the serial write operation. If fewer than 24 bits are written, the register will not be updated with new data. Figure 75 shows a more efficient way to write to the registers, using the AD9925's address automatic increment capability. Using this method, the lowest desired address is written first, followed by multiple 24-bit data-words. Each new 24-bit dataword will automatically be written to the next highest register address. By eliminating the need to write each 8-bit address, faster register loading is achieved. Continuous write operations may be used starting with any register location and may be used to write to as few as two registers or to as many as the entire register space.
8-BIT ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2
24-BIT DATA D3 D21 D22 D23
tDS
SCK 1 2 3 4
tDH
5 6 7 8 9 10 11 12 30 31 32
tLS
SL
tLH
NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HIGH OR LOW IN BETWEEN WRITE OPERATIONS. 2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA. 3. IF THE REGISTER LENGTH IS < 24 BITS, THEN DON'T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH. 4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE PARTICULAR REGISTER WRITTEN TO. SEE THE REGISTER UPDATES SECTION FOR MORE INFORMATION.
Figure 74. Serial Write Operation
DATA FOR STARTING REGISTER ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D22 D23 D0
DATA FOR NEXT REGISTER ADDRESS D1 D22 D23 D0 D1 D2
SCK
1
2
3
4
5
6
7
8
9
10
31
32
33
34
55
56
57
58
59
SL NOTES 1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS. 3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN). 4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
04637-0-062
Figure 75. Continuous Serial Write Operation
Rev. A | Page 59 of 96
04637-0-063
AD9925
Register Address BANK 1, BANK 2, and BANK 3
The AD9925 address space is divided into three different register banks, referred to as Register Bank 1, Register Bank 2, and Register Bank 3. Figure 76 illustrates how the three banks are divided. Register Bank 1 and Bank 2 are backward compatible with the AD9995 registers. Register Bank 1 contains the registers for the AFE, miscellaneous functions, VD/HD parameters, timing core, CLPOB masking, VSG patterns, and shutter functions. Register Bank 2 contains all of the information for the vertical pattern groups, vertical sequences, and field information. Register Bank 3 contains new registers for accessing the XV7 and XV8 functionality. These additional outputs allow the AD9925 to support newer CCDs that require 8-phases of vertical clocking. When writing to the AD9925, Addr 0x7F is used to specify which address bank is being written to. To write to Bank 1, a data value of 0 is written. To write to Bank 2, a data value of 1 is written. To write to Bank 3, a data value of 2 is written. Note that Register Bank 1 contains many unused addresses. Undefined addresses between Addr 0x00 and Addr 0x7F are considered Don't Cares, and it is acceptable if these addresses are filled in with all 0s during a continuous register write operation. However, the undefined addresses above 0x7F must not be written to, or the AD9925 may not operate properly. The exceptions are the FG_TRIG registers 0xE7, 0xEB, and 0xF2 through 0xF6, which may be written as specified on Page 43. Default values for Register Bank 2 and Bank 3 are undefined after power-up. Appropriate values should be written into these register banks to ensure proper operation. In applications where the XV7 and XV8 signals are not used, the Bank 3 registers should still be programmed with known values to prevent unpredictable behavior in the V-driver circuit.
REGISTER BANK 1 ADDR 0x00 AFE REGISTERS ADDR 0x10 MISCELLANEOUS REGISTERS ADDR 0x20 ADDR 0x30 ADDR 0x40 ADDR 0x50 VSG PATTERN REGISTERS ADDR 0x60 SHUTTER REGISTERS ADDR 0x7F ADDR 0x8F INVALID, DO NOT ACCESS ADDR 0xFF ADDR 0xFF SWITCH TO REGISTER BANK 2, BANK 3 ADDR 0xCF ADDR 0xD0 VD/HD REGISTERS TIMING CORE REGISTERS CLPOB MASK REGISTERS ADDR 0x7E ADDR 0x7F ADDR 0x80 ADDR 0x00
REGISTER BANK 2 ADDR 0x00
REGISTER BANK 3 VPAT0 TO VPAT9 REGISTERS FOR XV7, XV8 SIGNALS ADDR 0x4F ADDR 0x50 ADDR 0x77 VSEQ0 TO VSEQ9 REGISTERS FOR XV7, XV8 SIGNALS SWITCH TO REGISTER BANK 2, BANK 3
VPAT0 TO VPAT9 REGISTERS FOR XV1 TO XV6 SIGNALS
SWITCH TO REGISTER BANK 1, BANK 3 VSEQ0 TO VSEQ9 REGISTERS FOR XV1 TO XV6 SIGNALS
ADDR 0x7F
INVALID, DO NOT ACCESS
FIELD 0 TO FIELD 5 REGISTERS ADDR 0xFF
WRITE TO ADDRESS 0x7F TO SWITCH REGISTER BANKS
Figure 76. Layout of Internal Register Bank 1, Bank 2, and Bank 3
Rev. A | Page 60 of 96
04637-0-064
AD9925
Updating New Register Values
The AD9925's internal registers are updated at different times, depending on the particular register. Table 36 summarizes the four different types of register updates: 1. SCK Updated: Some of the registers in Bank 1 are updated as soon as the 24th data bit (D23) is written. These registers, shaded in gray in the Bank 1 register list, are used for functions that do not require gating with the next VD boundary, such as power-up and reset functions. The bank select register (Addr 0x7F in Bank 1 and Bank 2) is also SCK updated. VD Updated: Most of the registers in Bank 1, as well as the field registers in Bank 2, are updated at the next VD falling edge. By updating these values at the next VD edge, the current field will not be corrupted, and the new register values will be applied to the next field. Bank 1 register updates may be further delayed past the VD falling edge by using the UPDATE register (Addr 0x19). This will delay VD updates to any HD line in the field. Note that the Bank 2 field registers are not affected by the UPDATE register. 3. SG Line Updated: A few of the registers in Bank 1 are updated at the end of the SG active line, at the HD falling edge. These registers control the SUBCK signal, so that the SUBCK output will not update until after the SG line has been completed. These registers are crosshatched in the Bank 1 register list. SCP Updated: In Bank 2 and Bank 3, all of the vertical pattern group and vertical sequence registers (Addr 0x00 through Addr 0xCF, excluding Addr 0x7F) are updated at the next SCP, where they will be used. For example, in Figure 77, this field has selected Region 1 to use Vertical Sequence 3 for the vertical outputs. This means that a write to any of the Vertical Sequence 3 registers, or any of the vertical pattern group registers that are referenced by Vertical Sequence 3, will be updated at SCP1. If multiple writes are done to the same register, the last one done before SCP1 will be the one that is updated. Likewise, register writes to any Vertical Sequence 5 registers will be updated at SCP2, and register writes to any Vertical Sequence 8 registers will be updated at SCP3.
4.
2.
Table 36. Register Update Locations
Update Type SCK Updated VD Updated Register Bank Bank 1 Only Bank 1, Bank 2 Description Register is immediately updated when the 24th data bit (D23) is clocked in. Register is updated at the VD falling edge. VD updated registers in Bank 1 may be delayed further by using the UPDATE register at Addr 0x19 in Bank 1. Bank 2 updates will not be affected by the UPDATE register. Register is updated at the HD falling edge at the end of the SG active line. Register is updated at the next SCP when the register will be used.
SG Line Updated SCP Updated
Bank 1 Only Bank 2, Bank 3
SCK UPDATED SERIAL WRITE
VD UPDATED
SG UPDATED
SCP UPDATED
VD
HD SGLINE XSG
REGION 0 SCP 0
REGION 1 SCP 1 SCP 2
REGION 2
REGION 3 SCP 3 SCP 0
Figure 77. Register Update Locations (See Table 40 for Definitions)
Rev. A | Page 61 of 96
04637-0-065
XV1 TO XV6
USE VSEQ2
USE VSEQ3
USE VSEQ5
USE VSEQ8
AD9925 COMPLETE LISTING FOR REGISTER BANK 1
All registers are VD updated, except where noted. Light gray cells = SCK updated, and dark gray cells = SG line updated. Table 37. AFE Register Map
Address 00 01 02 03 Data Bit Content [11:0] [9:0] [7:0] [11:0] Default Value 7 0 80 4 Register Name OPRMODE VGAGAIN CLAMPLEVEL CTLMODE Register Description AFE Operation Modes (See Table 45 for detail) VGA Gain Optical Black Clamp Leve AFE Control Modes (See Table 46 for detail)
Table 38. Miscellaneous Register Map
Address 0A 0B 0C 0D 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E Data Bit Content [17:0] [17:0] [17:0] [17:0] [0] [0] [0] [0] [0] [0] [0] Default Value 3FF8 3FF8 0 3FF8 0 0 1 0 0 0 1 Register Name STBY1POL STBY2POL STBY3POL OCONTPOL SW_RST OUTCONTROL SYNCENABLE SYNCPOL SYNCSUSPEND TGCORE_RSTB OSC_PWRDOW N UNUSED TEST UPDATE PREVENTUPDATE MODE UNUSED OUTPUTPBLK DVCMODE Register Description Polarities for Output Signals during Standby 1 Mode. Polarities for Output Signals during Standby 2 Mode. Polarities for Output Signals during Standby 3 Mode. Polarities for Output Signals When OUTCONTROL = 0. Software Reset. 1: Reset all registers to default, then self clear back to 0. Output Control. 0: Make all outputs dc inactive. Configures Pin 52 as a SYNC Input (= 1) or CLPOB/PBLK Output (= 0). SYNC Active Polarity (0: Active Low). Suspend Clocks during SYNC Active (1: Suspend). Timing Core Reset Bar. 0: Reset TG Core, 1: Resume Operation. CLO Oscillator Power-Down (0: Oscillator Is Powered Down). Set to 0. Internal Use Only. Must be set to 0. Serial Update. Line (HD) in the field to update VD updated registers. Prevents the update of the VD updated registers. 1: Prevent Update. MODE Register. Set to 0. Assigns Output for Pin 52 When Configured as Output. 0: CLPOB, 1: PBLK. 1: Enable DVC Mode. VD counter will reset every 2 fields, instead of every field. VDLEN register should be programmed to the total number of lines contained in 2 fields, e.g., VDLEN = 525 lines will results in 262.5 lines in each field. 1: Invert the DCLK Output. Set to 0. Selects FG_TRIG Signal to VSUB Pin (See Page 43). Set to 0. H3HBLKOFF, Set to 1 to Enable H3/H4 Outputs during HBLK (See Page 19). Set to 0. Combines FG_TRIG and VSUB Signals (See Page 43). FG_TRIG Signal Enable (See Page 43). FG_TRIG Start Polarity. FG_TRIG First Toggle Position, Line Location. FG_TRIG First Toggle Position, Pixel Location. FG_TRIG Second Toggle Position, Line Location. FG_TRIG Second Toggle Position, Pixel Location.
[0] [11:0] [0] [23:0] [0] [0]
0 0 0 0 0 0
1F E7
[0] [2:0] [3] [5:4] [6] [7] [8] [3:0] [0] [11:0] [12:0] [11:0] [12:0]
0 0
INVERT_DCLK SHUT_EXTRA
EB F2 F3 F4 F5 F6
0 0 0 0 0 0
FG_TRIGEN FG_TRIGPOL FG_TRIGLIN1 FG_TRIGPIX1 FG_TRIGLIN2 FG_TRIGPIX2
Rev. A | Page 62 of 96
AD9925
Table 39. VD/HD Register Map
Address 20 21 22 23 Data Bit Content [0] [0] [11:0] [17:12] [11:0] Default Value 0 0 0 0 0 Register Name MASTER VDHDPOL HDRISE VDRISE SCP0 Register Description VD/HD Master or Slave Timing (0 = Slave Mode). VD/HD Active Polarity. 0 = Low and 1 = High. Rising Edge Location for HD. Rising Edge Location for VD. SCP0. Used for All Fields.
Table 40. Timing Core Register Map
Address 30 31 Data Bit Content [0] [0] [6:1] [12:7] [0] [6:1] [12:7] [0] [6:1] [12:7] [0] [1] [2:0] Default Value 0 1 0 20 1 0 20 1 0 20 0 0 1 Register Name CLIDIVIDE H1POL H1POSLOC H1NEGLOC H3POL H3POSLOC H3NEGLOC RGPOL RGPOSLOC RGNEGLOC H1RETIME H3RETIME H1DRV Register Description Divide CLI Input Clock by 2. 1 = Divide by 2. H1 Polarity. 0: Inversion, 1: No Inversion. H1 Positive Edge Location. H1 Negative Edge Location. H3 Polarity. 0: Inversion, 1: No Inversion. H3 Positive Edge Location. H3 Negative Edge Location. RG Polarity. 0: Inversion, 1: No Inversion. RG Positive Edge Location. RG Negative Edge Location. Retime H1/H3 HBLK to Internal H1/H3 Clocks. Preferred setting is 1 for each bit, which adds one cycle of delay to the programmed HBLK toggle positions. Drive Strength Control for H1. 0: Off. 1: 4.3 mA. 2: 8.6 mA. 3: 12.9 mA. 4: 17.2 mA. 5: 21.5 mA. 6: 25.8 mA. 7: 30.1 mA. Drive Strength Control for H2 (Same Values as H1DRV). Drive Strength Control for H3 (Same Values as H1DRV). Drive Strength Control for H4 (Same Values as H1DRV). Drive Strength Control for RG (Same Values as H1DRV). SHP Sampling Location. SHD Sampling Location. DOUT Phase Control. 0: DCLK Tracks DOUTPHASE. 1: DCLK Does Not Track DOUTPHASE, Remains Fixed with Regards to CLI Data Output Delay (tOD) with Respect to DCLK. 0: No Delay, 1: ~4 ns, 2: ~8 ns, and 3: ~12 ns. Controls HBLK Width as a Fraction of H1 to H4 Frequency. 0: same, 1: 1/2, 2: 1/4, 3: 1/6, 4: 1/8, 5: 1/10, 6: 1/12, and 7: 1/14.
32
33
34
35
36 37
[5:3] [8:6] [11:9] [14:12] [5:0] [11:6] [5:0] [6] [8:7]
1 1 1 1 24 0 0 0 2 0
H2DRV H3DRV H4DRV RGDRV SHPLOC SHDLOC DOUTPHASE DCLKMODE DOUTDLY HBLKWIDTH
38
[2:0]
Table 41. CLPOB Masking Register Map
Address 40 41 42 43 Data Bit Content [11:0] [23:12] [11:0] [23:12] [11:0] [11:0] [12] Default Value FFF FFF FFF FFF FFF FFF 0 Register Name CLPMASK0 CLPMASK1 CLPMASK2 CLPMASK3 CLPMASK4 CLPMASK5 CLPMASKTYPE Register Description CLPOB Line Masking Line No. 0, or Mask0 Range, Start Line CLPOB Line Masking Line No. 1, or Mask0 Range, End Line CLPOB Line Masking Line No. 2, or Mask1 Range, Start Line CLPOB Line Masking Line No. 3, or Mask1 Range, End Line CLPOB Line Masking Line No. 4, or Mask2 Range, Start Line CLPOB Line Masking Line No. 5, or Mask2 Range, End Line 0: CLPOB Line Masking, 1: Enable CLPOB Range Masking
Rev. A | Page 63 of 96
AD9925
Table 42. SG Pattern Register Map
Address 50 Data Bit Content [0] [1] [2] [3] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [5:0] [6] Default Value 1 1 1 1 FFF FFF FFF FFF FFF FFF FFF FFF 0 0 Register Name SGPOL_0 SGPOL_1 SGPOL_2 SGPOL_3 SGTOG1_0 SGTOG2_0 SGTOG1_1 SGTOG2_1 SGTOG1_2 SGTOG2_2 SGTOG1_3 SGTOG2_3 SGMASK_OVR SGMASKOVR_EN Register Description Start Polarity for SG Pattern No. 0. Start Polarity for SG Pattern No. 1. Start Polarity for SG Pattern No. 2. Start Polarity for SG Pattern No. 3. Pattern No. 0 Toggle Position 1. Pattern No. 0 Toggle Position 2. Pattern No. 1 Toggle Position 1. Pattern No. 1 Toggle Position 2. Pattern No. 2 Toggle Position 1. Pattern No. 2 Toggle Position 2. Pattern No. 3 Toggle Position 1. Pattern No. 3 Toggle Position 2. SGMASK Override. These values will immediately override the SG masking values located in the field registers. 0: Use SG Masking in Field Registers, 1: Enable SGMASK Override.
51 52 53 54 55
Table 43. Shutter Control Register Map
Address 60 Data Bit Content [4:0] Default Value 0 Register Name TRIGGER Register Description Trigger for VSUB [0], MSHUT [1], STROBE [2], Exposure [3], and Readout [4]. Note that to trigger the readout to automatically occur after the exposure period, both exposure and readout should be triggered together. Number of Fields to Suppress the SUBCK Pulses after the VSG Line. Number of Fields to Suppress the SUBCK and VSG Pulses. Set = 1 to disable the VD/HD outputs during exposure (when >1 field). Number of SUBCK Pulses to Suppress after VSG Line. Number of SUBCK Pulses per Field. SUBCK Pulse Start Polarity. First SUBCK Pulse. Toggle Position 1. First SUBCK Pulse. Toggle Position 2. Second SUBCK Pulse. Toggle Position 1. Second SUBCK Pulse. Toggle Position 2. VSUB Readout Mode. 0: Mode 0, 1: Mode 1. 0: Turn Off VSUB after Readout, 1: Keep VSUB On after Readout. VSUB Online Position. VSUB Active Polarity. MSHUT Active Polarity. MSHUT Manual Enable (Opens Shutter at Next VD Edge). MSHUT On Position--Line. MSHUT On Position--Pixel. MSHUT Off Position--Field. MSHUT Off Position--Line. MSHUT Off Position--Pixel. STROBE Active Polarity. STROBE On Position--Field. STROBE On Position--Line. STROBE On Position--Pixel. STROBE Off Position--Field. STROBE Off Position--Line. STROBE Off Position--Pixel. 13th Bit for SUBCK Toggle Position Placement.
61 62
[2:0] [11:0] [12] [11:0] [23:12] [0] [11:0] [23:12] [11:0] [23:12] [0] [1] [11:0] [12] [0] [1] [11:0] [23:12] [11:0] [11:0] [23:12] [0] [11:0] [11:0] [23:12] [11:0] [11:0] [23:12] [3:0]
2 0 0 0 0 1 FFF FFF FFF FFF 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0
READOUT EXPOSURE VDHDOFF SUBCKSUPPRESS SUBCKNUM SUBCKPOL SUBCK1TOG1 SUBCK1TOG2 SUBCK2TOG1 SUBCK2TOG2 VSUBMODE VSUBKEEPON VSUBON VSUBPOL MSHUTPOL MSHUTON MSHUTON_LN MSHUTON_PX MSHUTOFF_FD MSHUTOFF_LN MSHUTOFF_PX STROBPOL STROBON_FD STROBON_LN STROBON_PX STROBOFF_FD STROBOFF_LN STROBOFF_PX SUBCKTOG13
63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72
Rev. A | Page 64 of 96
AD9925
Table 44. Register Map Selection
Address 7F Data Bit Content [1:0] Default Value 0 Register Name BANKSELECT Register Description Register Bank Access for Bank 1, Bank 2, and Bank 3. 0: Bank 1, 1: Bank 2, 2: Bank 3, and 3: Bank 1.
Table 45. AFE Operation Register Detail
Address 00 Data Bit Content [1:0] [2] [3] [4] [5] [7:6] [8] [9] [11:10] Default Value 3 1 0 0 0 0 0 0 0 Name PWRDOWN CLPENABLE CLPSPEED FASTUPDATE PBLK_LVL TEST DCBYP TEST CDSGAIN Description 0: Normal Operation, 1: Standby 1, 2: Standby 2, 3: Standby 3. 0: Disable OB Clamp, 1: Enable OB Clamp. 0: Select Normal OB Clamp Settling, 1: Select Fast OB Clamp Settling. 1: Select Temporary Fast Clamping When VGA Gain Is Updated. DOUT Value during PBLK: 0: Blank to 0, 1: Blank to Clamp Level. Test Operation Only. Set to 0. 0: Enable DC Restore Circuit, 1: Bypass DC Restore Circuit during PBLK. Test Use Only. Set to 0. 0: 0 dB, 1: 2 dB, 2: 4 dB, and 3: 0 dB.
Table 46. AFE Control Register Detail
Address 03 Data Bit Content [1:0] [2] [3] [4] [5] Default Value 0 1 0 0 0 Name TEST TEST DOUTDISABLE DOUTLATCH GRAYENCODE Description Test Use Only. Set to 0. Test Use Only. Recommended setting is 0. 0 = Data Outputs Are Driven, 1 = Data Outputs Are Three-Stated. 0 = Latch Data Outputs with DOUT Phase, 1 = Output Latch Transparent. 0 = Binary Encode Data Outputs, 1 = Gray Encode Data Outputs.
Rev. A | Page 65 of 96
AD9925 COMPLETE LISTING FOR REGISTER BANK 2
All vertical pattern group and vertical sequence registers are SCP updated, and all field registers are VD updated. Default register values are undefined. Table 47. Vertical Pattern Group 0 (VPAT0) Register Map
Address 00 Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_0 UNUSED VPATLEN_0 Register Description VPAT0 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT0. Note: If using VPAT0 as a second vertical sequence in the VSG active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
01 02 03 04 05 06 07 08 09 0A 0B
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_0 XV1TOG2_0 XV1TOG3_0 XV2TOG1_0 XV2TOG2_0 XV2TOG3_0 XV3TOG1_0 XV3TOG2_0 XV3TOG3_0 XV4TOG1_0 XV4TOG2_0 XV4TOG3_0 XV5TOG1_0 XV5TOG2_0 XV5TOG3_0 XV6TOG1_0 XV6TOG2_0 XV6TOG3_0 FREEZE1_0 RESUME1_0 FREEZE2_0 RESUME2_0
Rev. A | Page 66 of 96
AD9925
Table 48. Vertical Pattern Group 1 (VPAT1) Register Map
Address 0C Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_1 UNUSED VPATLEN_1 Register Description VPAT1 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT1. Note: If using VPAT1 as a second vertical sequence in the VSG active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
0D 0E 0F 10 11 12 13 14 15 16 17
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_1 XV1TOG2_1 XV1TOG3_1 XV2TOG1_1 XV2TOG2_1 XV2TOG3_1 XV3TOG1_1 XV3TOG2_1 XV3TOG3_1 XV4TOG1_1 XV4TOG2_1 XV4TOG3_1 XV5TOG1_1 XV5TOG2_1 XV5TOG3_1 XV6TOG1_1 XV6TOG2_1 XV6TOG3_1 FREEZE1_1 RESUME1_1 FREEZE2_1 RESUME2_1
Rev. A | Page 67 of 96
AD9925
Table 49. Vertical Pattern Group 2 (VPAT2) Register Map
Address 18 Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_2 UNUSED VPATLEN_2 Register Description VPAT2 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT2. Note: If using VPAT2 as a second vertical sequence in the VSG active line, this value is the start position for second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
19 1A 1B 1C 1D 1E 1F 20 21 22 23
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_2 XV1TOG2_2 XV1TOG3_2 XV2TOG1_2 XV2TOG2_2 XV2TOG3_2 XV3TOG1_2 XV3TOG2_2 XV3TOG3_2 XV4TOG1_2 XV4TOG2_2 XV4TOG3_2 XV5TOG1_2 XV5TOG2_2 XV5TOG3_2 XV6TOG1_2 XV6TOG2_2 XV6TOG3_2 FREEZE1_2 RESUME1_2 FREEZE2_2 RESUME2_2
Rev. A | Page 68 of 96
AD9925
Table 50. Vertical Pattern Group 3 (VPAT3) Register Map
Address 24 Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_3 UNUSED VPATLEN_3 Register Description VPAT3 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT3. Note: If using VPAT3 as a second vertical sequence in the VSG active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
25 26 27 28 29 2A 2B 2C 2D 2E 2F
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_3 XV1TOG2_3 XV1TOG3_3 XV2TOG1_3 XV2TOG2_3 XV2TOG3_3 XV3TOG1_3 XV3TOG2_3 XV3TOG3_3 XV4TOG1_3 XV4TOG2_3 XV4TOG3_3 XV5TOG1_3 XV5TOG2_3 XV5TOG3_3 XV6TOG1_3 XV6TOG2_3 XV6TOG3_3 FREEZE1_3 RESUME1_3 FREEZE2_3 RESUME2_3
Rev. A | Page 69 of 96
AD9925
Table 51. Vertical Pattern Group 4 (VPAT4) Register Map
Address 30 Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_4 UNUSED VPATLEN_4 Register Description VPAT4 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused . Total Length of VPAT4. Note: If using VPAT4 as a second vertical sequence in the VSG active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
31 32 33 34 35 36 37 38 39 3A 3B
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_4 XV1TOG2_4 XV1TOG3_4 XV2TOG1_4 XV2TOG2_4 XV2TOG3_4 XV3TOG1_4 XV3TOG2_4 XV3TOG3_4 XV4TOG1_4 XV4TOG2_4 XV4TOG3_4 XV5TOG1_4 XV5TOG2_4 XV5TOG3_4 XV6TOG1_4 XV6TOG2_4 XV6TOG3_4 FREEZE1_4 RESUME1_4 FREEZE2_4 RESUME2_4
Rev. A | Page 70 of 96
AD9925
Table 52. Vertical Pattern Group 5 (VPAT5) Register Map
Address 3C Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_5 UNUSED VPATLEN_5 Register Description VPAT5 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT5. Note: If using VPAT5 as a second vertical sequence in the VSG active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
3D 3E 3F 40 41 42 43 44 45 46 47
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_5 XV1TOG2_5 XV1TOG3_5 XV2TOG1_5 XV2TOG2_5 XV2TOG3_5 XV3TOG1_5 XV3TOG2_5 XV3TOG3_5 XV4TOG1_5 XV4TOG2_5 XV4TOG3_5 XV5TOG1_5 XV5TOG2_5 XV5TOG3_5 XV6TOG1_5 XV6TOG2_5 XV6TOG3_5 FREEZE1_5 RESUME1_5 FREEZE2_5 RESUME2_5
Rev. A | Page 71 of 96
AD9925
Table 53. Vertical Pattern Group 6 (VPAT6) Register Map
Address 48 Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_6 UNUSED VPATLEN_6 Register Description VPAT6 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT6. Note: If using VPAT6 as a second vertical sequence in the VSG Active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
49 4A 4B 4C 4D 4E 4F 50 51 52 53
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_6 XV1TOG2_6 XV1TOG3_6 XV2TOG1_6 XV2TOG2_6 XV2TOG3_6 XV3TOG1_6 XV3TOG2_6 XV3TOG3_6 XV4TOG1_6 XV4TOG2_6 XV4TOG3_6 XV5TOG1_6 XV5TOG2_6 XV5TOG3_6 XV6TOG1_6 XV6TOG2_6 XV6TOG3_6 FREEZE1_6 RESUME1_6 FREEZE2_6 RESUME2_6
Rev. A | Page 72 of 96
AD9925
Table 54. Vertical Pattern Group 7 (VPAT7) Register Map
Address 54 Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_7 UNUSED VPATLEN_7 Register Description VPAT7 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT7. Note: If using VPAT7 as a second vertical sequence in the VSG active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
55 56 57 58 59 5A 5B 5C 5D 5E 5F
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_7 XV1TOG2_7 XV1TOG3_7 XV2TOG1_7 XV2TOG2_7 XV2TOG3_7 XV3TOG1_7 XV3TOG2_7 XV3TOG3_7 XV4TOG1_7 XV4TOG2_7 XV4TOG3_7 XV5TOG1_7 XV5TOG2_7 XV5TOG3_7 XV6TOG1_7 XV6TOG2_7 XV6TOG3_7 FREEZE1_7 RESUME1_7 FREEZE2_7 RESUME2_7
Rev. A | Page 73 of 96
AD9925
Table 55. Vertical Pattern Group 8 (VPAT8) Register Map
Address 60 Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_8 UNUSED VPATLEN_8 Register Description VPAT8 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT8. Note: If using VPAT8 as a second vertical sequence in the VSG active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV1 Toggle Position 4. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV2 Toggle Position 4. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV3 Toggle Position 4. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV4 Toggle Position 4. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV5 Toggle Position 4. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV6 Toggle Position 4. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2. Unused.
61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_8 XV1TOG2_8 XV1TOG3_8 XV1TOG4_8 XV2TOG1_8 XV2TOG2_8 XV2TOG3_8 XV2TOG4_8 XV3TOG1_8 XV3TOG2_8 XV3TOG3_8 XV3TOG4_8 XV4TOG1_8 XV4TOG2_8 XV4TOG3_8 XV4TOG4_8 XV5TOG1_8 XV5TOG2_8 XV5TOG3_8 XV5TOG4_8 XV6TOG1_8 XV6TOG2_8 XV6TOG3_8 XV6TOG4_8 FREEZE1_8 RESUME1_8 FREEZE2_8 RESUME2_8 UNUSED
Rev. A | Page 74 of 96
AD9925
Table 56. Vertical Pattern Group 9 (VPAT9) Register Map
Address 70 Data Bit Content [5:0] [11:6] [23:12] Default Value X X X Register Name VPOL_9 UNUSED VPATLEN_9 Register Description VPAT9 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length of VPAT9. Note: If using VPAT9 as a second vertical sequence in the VSG active line, this value is the start position for the second vertical sequence. XV1 Toggle Position 1. XV1 Toggle Position 2. XV1 Toggle Position 3. XV1 Toggle Position 4. XV2 Toggle Position 1. XV2 Toggle Position 2. XV2 Toggle Position 3. XV2 Toggle Position 4. XV3 Toggle Position 1. XV3 Toggle Position 2. XV3 Toggle Position 3. XV3 Toggle Position 4. XV4 Toggle Position 1. XV4 Toggle Position 2. XV4 Toggle Position 3. XV4 Toggle Position 4. XV5 Toggle Position 1. XV5 Toggle Position 2. XV5 Toggle Position 3. XV5 Toggle Position 4. XV6 Toggle Position 1. XV6 Toggle Position 2. XV6 Toggle Position 3. XV6 Toggle Position 4. XV1 to XV6 Freeze Position 1. XV1 to XV6 Resume Position 1. XV1 to XV6 Freeze Position 2. XV1 to XV6 Resume Position 2.
71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E
[11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12]
X X X X X X X X X X X X X X X X X X X X X X X X X X X X
XV1TOG1_9 XV1TOG2_9 XV1TOG3_9 XV1TOG4_9 XV2TOG1_9 XV2TOG2_9 XV3TOG3_9 XV3TOG4_9 XV3TOG1_9 XV4TOG2_9 XV4TOG3_9 XV4TOG4_9 XV5TOG1_9 XV5TOG2_9 XV5TOG3_9 XV6TOG4_9 XV6TOG1_9 XV6TOG2_9 XV6TOG3_9 XV6TOG4_9 XV6TOG1_9 XV6TOG2_9 XV6TOG3_9 XV6TOG4_9 FREEZE1_9 RESUME1_9 FREEZE2_9 RESUME2_9
Table 57. Register Map Selection (SCK Updated Register)
Address 7F Data Bit Content [1:0] Default Value 0 Register Name BANKSELECT Register Description Register Bank Access for Bank 1, Bank 2, and Bank 3.
Rev. A | Page 75 of 96
AD9925
Table 58. Vertical Sequence 0 (VSEQ0) Register Map
Address 80 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_0 CLPOBPOL_0 PBLKPOL_0 VPATSEL_0 VMASK_0 HBLKALT_0 HDLEN13_0 UNUSED VPATREPO_0 VPATREPE_0 VPATSTART_0 HDLEN_0 PBLKTOG1_0 PBLKTOG2_0 HBLKTOG1_0 HBLKTOG2_0 HBLKTOG3_0 HBLKTOG4_0 HBLKTOG5_0 HBLKTOG6_0 CLPOBTOG1_0 CLPOBTOG2_0 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 0. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME Registers). Enable HBLK Alternation. 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 0. PBLK Toggle Position 1 for Vertical Sequence 0. PBLK Toggle Position 2 for Vertical Sequence 0. HBLK Toggle Position 1 for Vertical Sequence 0. HBLK Toggle Position 2 for Vertical Sequence 0. HBLK Toggle Position 3 for Vertical Sequence 0. HBLK Toggle Position 4 for Vertical Sequence 0. HBLK Toggle Position 5 for Vertical Sequence 0. HBLK Toggle Position 6 for Vertical Sequence 0. CLPOB Toggle Position 1 for Vertical Sequence 0. CLPOB Toggle Position 2 for Vertical Sequence 0.
81
82 83 84 85 86 87
Table 59. Vertical Sequence 1 (VSEQ1) Register Map
Address 88 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0]| [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_1 CLPOBPOL_1 PBLKPOL_1 VPATSEL_1 VMASK_1 HBLKALT_1 HDLEN13_1 UNUSED VPATREPO_1 VPATREPE_1 VPATSTART_1 HDLEN_1 PBLKTOG1_1 PBLKTOG2_1 HBLKTOG1_1 HBLKTOG2_1 HBLKTOG3_1 HBLKTOG4_1 HBLKTOG5_1 HBLKTOG6_1 CLPOBTOG1_1 CLPOBTOG2_1 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 1. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME Registers). Enable HBLK Alternation. 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 1. PBLK Toggle Position 1 for Vertical Sequence 1. PBLK Toggle Position 2 for Vertical Sequence 1. HBLK Toggle Position 1 for Vertical Sequence 1. HBLK Toggle Position 2 for Vertical Sequence 1. HBLK Toggle Position 3 for Vertical Sequence 1. HBLK Toggle Position 4 for Vertical Sequence 1. HBLK Toggle Position 5 for Vertical Sequence 1. HBLK Toggle Position 6 for Vertical Sequence 1. CLPOB Toggle Position 1 for Vertical Sequence 1. CLPOB Toggle Position 2 for Vertical Sequence 1.
89 8A 8B 8C 8D 8E 8F
Rev. A | Page 76 of 96
AD9925
Table 60. Vertical Sequence 2 (VSEQ2) Register Map
Address 90 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_2 CLPOBPOL_2 PBLKPOL_2 VPATSEL_2 VMASK_2 HBLKALT_2 HDLEN13_2 UNUSED VPATREPO_2 VPATREPE_2 VPATSTART_2 HDLEN_2 PBLKTOG1_2 PBLKTOG2_2 HBLKTOG1_2 HBLKTOG2_2 HBLKTOG3_2 HBLKTOG4_2 HBLKTOG5_2 HBLKTOG6_2 CLPOBTOG1_2 CLPOBTOG2_2 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 2. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME Registers). Enable HBLK Alternation . 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 2. PBLK Toggle Position 1 for Vertical Sequence 2. PBLK Toggle Position 2 for Vertical Sequence 2. HBLK Toggle Position 1 for Vertical Sequence 2. HBLK Toggle Position 2 for Vertical Sequence 2. HBLK Toggle Position 3 for Vertical Sequence 2. HBLK Toggle Position 4 for Vertical Sequence 2. HBLK Toggle Position 5 for Vertical Sequence 2. HBLK Toggle Position 6 for Vertical Sequence 2. CLPOB Toggle Position 1 for Vertical Sequence 2. CLPOB Toggle Position 2 for Vertical Sequence 2.
91 92 93 94 95 96 97
Table 61. Vertical Sequence 3 (VSEQ3) Register Map
Address 98 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_3 CLPOBPOL_3 PBLKPOL_3 VPATSEL_3 VMASK_3 HBLKALT_3 HDLEN13_3 UNUSED VPATREPO_3 VPATREPE_3 VPATSTART_3 HDLEN_3 PBLKTOG1_3 PBLKTOG2_3 HBLKTOG1_3 HBLKTOG2_3 HBLKTOG3_3 HBLKTOG4_3 HBLKTOG5_3 HBLKTOG6_3 CLPOBTOG1_3 CLPOBTOG2_3 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 3. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME Registers). Enable HBLK Alternation 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 3. PBLK Toggle Position 1 for Vertical Sequence 3. PBLK Toggle Position 2 for Vertical Sequence 3. HBLK Toggle Position 1 for Vertical Sequence 3. HBLK Toggle Position 2 for Vertical Sequence 3. HBLK Toggle Position 3 for Vertical Sequence 3. HBLK Toggle Position 4 for Vertical Sequence 3. HBLK Toggle Position 5 for Vertical Sequence 3. HBLK Toggle Position 6 for Vertical Sequence 3. CLPOB Toggle Position 1 for Vertical Sequence 3. CLPOB Toggle Position 2 for Vertical Sequence 3.
99 9A 9B 9C 9D 9E 9F
Rev. A | Page 77 of 96
AD9925
Table 62. Vertical Sequence 4 (VSEQ4) Register Map
Address A0 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] A2 A3 A4 A5 A6 A7 [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_4 CLPOBPOL_4 PBLKPOL_4 VPATSEL_4 VMASK_4 HBLKALT_4 HDLEN13_4 UNUSED VPATREPO_4 VPATREPE_4 VPATSTART_4 HDLEN_4 PBLKTOG1_4 PBLKTOG2_4 HBLKTOG1_4 HBLKTOG2_4 HBLKTOG3_4 HBLKTOG4_4 HBLKTOG5_4 HBLKTOG6_4 CLPOBTOG1_4 CLPOBTOG2_4 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 4. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME Registers). Enable HBLK Alternation. 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 4. PBLK Toggle Position 1 for Vertical Sequence 4. PBLK Toggle Position 2 for Vertical Sequence 4. HBLK Toggle Position 1 for Vertical Sequence 4. HBLK Toggle Position 2 for Vertical Sequence 4. HBLK Toggle Position 3 for Vertical Sequence 4. HBLK Toggle Position 4 for Vertical Sequence 4. HBLK Toggle Position 5 for Vertical Sequence 4. HBLK Toggle Position 6 for Vertical Sequence 4. CLPOB Toggle Position 1 for Vertical Sequence 4. CLPOB Toggle Position 2 for Vertical Sequence 4.
A1
Table 63. Vertical Sequence 5 (VSEQ5)Register Map
Address A8 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] AA AB AC AD AE AF [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_5 CLPOBPOL_5 PBLKPOL_5 VPATSEL_5 VMASK_5 HBLKALT_5 HDLEN13_5 UNUSED VPATREPO_5 VPATREPE_5 VPATSTART_5 HDLEN_5 PBLKTOG1_5 PBLKTOG2_5 HBLKTOG1_5 HBLKTOG2_5 HBLKTOG3_5 HBLKTOG4_5 HBLKTOG5_5 HBLKTOG6_5 CLPOBTOG1_5 CLPOBTOG2_5 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 5. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME registers). Enable HBLK Alternation. 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 5. PBLK Toggle Position 1 for Vertical Sequence 5. PBLK Toggle Position 2 for Vertical Sequence 5. HBLK Toggle Position 1 for Vertical Sequence 5. HBLK Toggle Position 2 for Vertical Sequence 5. HBLK Toggle Position 3 for Vertical Sequence 5. HBLK Toggle Position 4 for Vertical Sequence 5. HBLK Toggle Position 5 for Vertical Sequence 5. HBLK Toggle Position 6 for Vertical Sequence 5. CLPOB Toggle Position 1 for Vertical Sequence 5. CLPOB Toggle Position 2 for Vertical Sequence 5.
A9
Rev. A | Page 78 of 96
AD9925
Table 64. Vertical Sequence 6 (VSEQ6) Register Map
Address B0 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_6 CLPOBPOL_6 PBLKPOL_6 VPATSEL_6 VMASK_6 HBLKALT_6 HDLEN13_6 UNUSED VPATREPO_6 V PATREPE_6 VPATSTART_6 HDLEN_6 PBLKTOG1_6 PBLKTOG2_6 HBLKTOG1_6 HBLKTOG2_6 HBLKTOG3_6 HBLKTOG4_6 HBLKTOG5_6 HBLKTOG6_6 CLPOBTOG1_6 CLPOBTOG2_6 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 6. Enable Masking of Vertical outputs (specified by FREEZE/RESUME registers). Enable HBLK Alternation. 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 6. PBLK Toggle Position 1 for Vertical Sequence 6. PBLK Toggle Position 2 for Vertical Sequence 6. HBLK Toggle Position 1 for Vertical Sequence 6. HBLK Toggle Position 2 for Vertical Sequence 6. HBLK Toggle Position 3 for Vertical Sequence 6. HBLK Toggle Position 4 for Vertical Sequence 6. HBLK Toggle Position 5 for Vertical Sequence 6. HBLK Toggle Position 6 for Vertical Sequence 6. CLPOB Toggle Position 1 for Vertical Sequence 6. CLPOB Toggle Position 2 for Vertical Sequence 6.
B1 B2 B3 B4 B5 B6 B7
Table 65. Vertical Sequence 7 (VSEQ7) Register Map
Address B8 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_7 CLPOBPOL_7 PBLKPOL_7 VPATSEL_7 VMASK_7 HBLKALT_7 HDLEN13_7 UNUSED VPATREPO_7 VPATREPE_7 VPATSTART_7 HDLEN_7 PBLKTOG1_7 PBLKTOG2_7 HBLKTOG1_7 HBLKTOG2_7 HBLKTOG3_7 HBLKTOG4_7 HBLKTOG5_7 HBLKTOG6_7 CLPOBTOG1_7 CLPOBTOG2_7 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 7. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME Registers). Enable HBLK Alternation. 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 7. PBLK Toggle Position 1 for Vertical Sequence 7. PBLK Toggle Position 2 for Vertical Sequence 7. HBLK Toggle Position 1 for Vertical Sequence 7. HBLK Toggle Position 2 for Vertical Sequence 7. HBLK Toggle Position 3 for Vertical Sequence 7. HBLK Toggle Position 4 for Vertical Sequence 7. HBLK Toggle Position 5 for Vertical Sequence 7. HBLK Toggle Position 6 for Vertical Sequence 7. CLPOB Toggle Position 1 for Vertical Sequence 7. CLPOB Toggle Position 2 for Vertical Sequence 7.
B9 BA BB BC BD BE BF
Rev. A | Page 79 of 96
AD9925
Table 66. Vertical Sequence 8 (VSEQ8) Register Map
Address C0 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_8 CLPOBPOL_8 PBLKPOL_8 VPATSEL_8 VMASK_8 HBLKALT_8 HDLEN13_8 UNUSED VPATREPO_8 VPATREPE_8 VPATSTART_8 HDLEN_8 PBLKTOG1_8 PBLKTOG2_8 HBLKTOG1_8 HBLKTOG2_8 HBLKTOG3_8 HBLKTOG4_8 HBLKTOG5_8 HBLKTOG6_8 CLPOBTOG1_8 CLPOBTOG2_8 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 8. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME Registers). Enable HBLK Alternation. 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 8. PBLK Toggle Position 1 for Vertical Sequence 8. PBLK Toggle Position 2 for Vertical Sequence 8. HBLK Toggle Position 1 for Vertical Sequence 8. HBLK Toggle Position 2 for Vertical Sequence 8. HBLK Toggle Position 3 for Vertical Sequence 8. HBLK Toggle Position 4 for Vertical Sequence 8. HBLK Toggle Position 5 for Vertical Sequence 8. HBLK Toggle Position 6 for Vertical Sequence 8. CLPOB Toggle Position 1 for Vertical Sequence 8. CLPOB Toggle Position 2 for Vertical Sequence 8.
C1 C2 C3 C4 C5 C6 C7
Table 67. Vertical Sequence 9 (VSEQ9) Register Map
Address C8 Data Bit Content [1:0] [2] [3] [7:4] [9:8] [11:10] [12] [23:12] [11:0] [23:12] CA CB CC CD CE CF [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X Register Name HBLKMASK_9 CLPOBPOL_9 PBLKPOL_9 VPATSEL_9 VMASK_9 HBLKALT_9 HDLEN13_9 UNUSED VPATREPO_9 VPATREPE_9 VPATSTART_9 HDLEN_9 PBLKTOG1_9 PBLKTOG2_9 HBLKTOG1_9 HBLKTOG2_9 HBLKTOG3_9 HBLKTOG4_9 HBLKTOG5_9 HBLKTOG6_9 CLPOBTOG1_9 CLPOBTOG2_9 Register Description Masking Polarity during HBLK. H1 [0], H3 [1]. CLPOB Start Polarity. PBLK Start Polarity. Selected Vertical Pattern Group for Vertical Sequence 9. Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME registers). Enable HBLK Alternation. 13th Bit for HD Length Counter Allows HD Length up to 8191 Pixels. Unused. Number of Selected Vertical Pattern Group Repetitions for Odd Lines. Number of Selected Vertical Pattern Group Repetitions for Even Lines. Start Position in the Line for the Selected Vertical Pattern Group. HD Line Length (Number of Pixels) for Vertical Sequence 9. PBLK Toggle Position 1 for Vertical Sequence 9. PBLK Toggle Position 2 for Vertical Sequence 9. HBLK Toggle Position 1 for Vertical Sequence 9. HBLK Toggle Position 2 for Vertical Sequence 9. HBLK Toggle Position 3 for Vertical Sequence 9. HBLK Toggle Position 4 for Vertical Sequence 9. HBLK Toggle Position 5 for Vertical Sequence 9. HBLK Toggle Position 6 for Vertical Sequence 9. CLPOB Toggle Position 1 for Vertical Sequence 9. CLPOB Toggle Position 2 for Vertical Sequence 9.
C9
Rev. A | Page 80 of 96
AD9925
Table 68. Field 0 Register Map
Address D0 Data Bit Content [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [22] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Register Name VSEQSEL0_0 SWEEP0_0 MULTI0_0 VSEQSEL1_0 SWEEP1_0 MULTI1_0 VSEQSEL2_0 SWEEP2_0 MULTI2_0 VSEQSEL3_0 SWEEP3_0 MULTI3_0 VSEQSEL4_0 SWEEP4_0 MULTI4_0 VSEQSEL5_0 SWEEP5_0 MULTI5_0 VSEQSEL6_0 SWEEP6_0 MULTI6_0 UNUSED SCP1_0 SCP2_0 SCP3_0 SCP4_0 VDLEN_0 HDLAST_0 VPATSECOND_0 SGMASK_0 SGPATSEL_0 HDLAST13_0 SGLINE1_0 SGLINE2_0 SCP5_0 SCP6_0 Register Description Selected Vertical Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. Vertical Sequence Change Position No. 1 for Field 0. Vertical Sequence Change Position No. 2 for Field 0. Vertical Sequence Change Position No. 3 for Field 0. Vertical Sequence Change Position No. 4 for Field 0. VD Field Length (Number of Lines) for Field 0. HD Line Length (Number of Pixels) for Last Line in Field 0. Selected Second Vertical Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. MSB for 13-Bit Last Line Length VSG Active Line 1. VSG Active Line 2 (If No Second Line Is Needed, Set to Same as Line 1 or Maximum). Vertical Sequence Change Position No. 5 for Field 0. Vertical Sequence Change Position No. 6 for Field 0.
D1
D2 D3 D4 D5
D6
X X X X
D7
Rev. A | Page 81 of 96
AD9925
Table 69. Field 1 Register Map
Address D8 Data Bit Content [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [22] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Register Name VSEQSEL0_1 SWEEP0_1 MULTI0_1 VSEQSEL1_1 SWEEP1_1 MULTI1_1 VSEQSEL2_1 SWEEP2_1 MULTI2_1 VSEQSEL3_1 SWEEP3_1 MULTI3_1 VSEQSEL4_1 SWEEP4_1 MULTI4_1 VSEQSEL5_1 SWEEP5_1 MULTI5_1 VSEQSEL6_1 SWEEP6_1 MULTI6_1 UNUSED SCP1_1 SCP2_1 SCP3_1 SCP4_1 VDLEN_1 HDLAST_1 VPATSECOND_1 SGMASK_1 SGPATSEL_1 HDLAST13_1 SGLINE1_1 SGLINE2_1 SCP5_1 SCP6_1 Register Description Selected Vertical Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. Vertical Sequence Change Position No. 1 for Field 1. Vertical Sequence Change Position No. 2 for Field 1. Vertical Sequence Change Position No. 3 for Field 1. Vertical Sequence Change Position No. 4 for Field 1. VD Field Length (Number of Lines) for Field 1. HD Line Length (Number of Pixels) for Last Line in Field 1. Selected Second Vertical Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. MSB for 13-Bit Last Line Length VSG Active Line 1. VSG Active Line 2. (If No Second Line Is Needed, Set to Same as Line 1 or Maximum). Vertical Sequence Change Position No. 5 for Field 1. Vertical Sequence Change Position No. 6 for Field 1.
D9
DA DB DC DD
DE
DF
Rev. A | Page 82 of 96
AD9925
Table 70. Field 2 Register Map
Address E0 Data Bit Content [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [22] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Register Name VSEQSEL_2 SWEEP0_2 MULTI0_2 VSEQSEL1_2 SWEEP1_2 MULTI1_2 VSEQSEL2_2 SWEEP2_2 MULTI2_2 VSEQSEL3_2 SWEEP3_2 MULTI3_2 VSEQSEL4_2 SWEEP4_2 MULTI4_2 VSEQSEL5_2 SWEEP5_2 MULTI5_2 VSEQSEL6_2 SWEEP6_2 MULTI6_2 UNUSED SCP1_2 SCP2_2 SCP3_2 SCP4_2 VDLEN0_2 HDLAST_2 VPATSECOND_2 SGMASK_2 SGPATSEL_2 HDLAST13_2 SGLINE1_2 SGLINE2_2 SCP5_2 SCP6_2 Register Description Selected Vertical Sequence for Region 0 Sequence for Region 1. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 2. Vertical Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. Vertical Sequence Change Position No. 1 for Field 2. Vertical Sequence Change Position No. 2 for Field 2. Vertical Sequence Change Position No. 3 for Field 2. Vertical Sequence Change Position No. 4 for Field 2. VD Field Length (Number of Lines) for Field 2. HD Line Length (Number of Pixels) for Last Line in Field 2. Selected Second Vertical Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. MSB for 13-Bit Last Line Length VSG Active Line 1. VSG Active Line 2. (If No Second Line Is Needed, Set to Same as Line 1 or Maximum). Vertical Sequence Change Position No. 5 for Field 2. Vertical Sequence Change Position No. 6 for Field 2.
E1
E2 E3 E4 E5
E6
E7
Rev. A | Page 83 of 96
AD9925
Table 71. Field 3 Register Map
Address E8 Data Bit Content [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [22] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Register Name VSEQSEL_3 SWEEP0_3 MULTI0_3 VSEQSEL1_3 SWEEP1_3 MULTI1_3 VSEQSEL2_3 SWEEP2_3 MULTI2_3 VSEQSEL3_3 SWEEP3_3 MULTI3_3 VSEQSEL4_3 SWEEP4_3 MULTI4_3 VSEQSEL5_3 SWEEP5_3 MULTI5_3 VSEQSEL6_3 SWEEP6_3 MULTI6_3 UNUSED SCP1_3 SCP2_3 SCP3_3 SCP4_3 VDLEN_3 HDLAST_3 VPATSECOND_3 SGMASK_3 SGPATSEL_3 HDLAST13_3 SGLINE1_3 SGLINE2_3 SCP5_3 SCP6_3 Register Description Selected Vertical Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused . Vertical Sequence Change Position No. 1 for Field 3. Vertical Sequence Change Position No. 2 for Field 3. Vertical Sequence Change Position No. 3 for Field 3. Vertical Sequence Change Position No. 4 for Field 3. VD Field Length (Number of Lines) for Field 3. HD Line Length (Number of Pixels) for Last Line in Field 3. Selected Second Vertical Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. MSB for 13-Bit Last Line Length VSG Active Line 1. VSG Active Line 2. (If No Second Line Is Needed, Set to Same as Line 1 or Maximum). Vertical Sequence Change Position No. 5 for Field 3. Vertical Sequence Change Position No. 6 for Field 3.
E9
EA EB EC ED
EE
EF
Rev. A | Page 84 of 96
AD9925
Table 72. Field 4 Register Map
Address F0 Data Bit Content [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [22] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Register Name VSEQSEL0_4 SWEEP0_4 MULTI0_4 VSEQSEL1_4 SWEEP1_4 MULTI1_4 VSEQSEL2_4 SWEEP2_4 MULTI2_4 VSEQSEL3_4 SWEEP3_4 MULTI3_4 VSEQSEL4_4 SWEEP4_4 MULTI4_4 VSEQSEL5_4 SWEEP5_4 MULTI5_4 VSEQSEL6_4 SWEEP6_4 MULTI6_4 UNUSED SCP1_4 SCP2_4 SCP3_4 SCP4_4 VDLEN_4 HDLAST_4 VPATSECOND_4 SGMASK_4 SGPATSEL_4 HDLAST13_4 SGLINE1_4 SGLINE2_4 SCP5_4 SCP6_4 Register Description Selected Vertical Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. Vertical Sequence Change Position No. 1 for Field 4. Vertical Sequence Change Position No. 2 for Field 4. Vertical Sequence Change Position No. 3 for Field 4. Vertical Sequence Change Position No. 4 for Field 4. VD Field Length (Number of Lines) for Field 4. HD Line Length (Number of Pixels) for Last Line in Field 4. Selected Second Vertical Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. MSB for 13-Bit Last Line Length VSG Active Line 1. VSG Active Line 2. (If No Second Line Is Needed, Set to Same as Line 1 or Maximum). Vertical Sequence Change Position No. 5 for Field 4. Vertical Sequence Change Position No. 6 for Field 4.
F1
F2 F3 F4 F5
F6
F7
Rev. A | Page 85 of 96
AD9925
Table 73. Field 5 Register Map
Address F8 Data Bit Content [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [22] [11:0] [23:12] [11:0] [23:12] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Register Name VSEQSEL0_5 SWEEP0_5 MULTI0_5 VSEQSEL1_5 SWEEP1_5 MULTI1_5 VSEQSEL2_5 SWEEP2_5 MULTI2_5 VSEQSEL3_5 SWEEP3_5 MULTI3_5 VSEQSEL4_5 SWEEP4_5 MULTI4_5 VSEQSEL5_5 SWEEP5_5 MULTI5_5 VSEQSEL6_5 SWEEP6_5 MULTI6_5 UNUSED SCP1_5 SCP2_5 SCP3_5 SCP4_5 VDLEN_5 HDLAST_5 VPATSECOND_5 SGMASK_5 SGPATSEL_5 HDLAST13_5 SGLINE1_5 SGLINE2_5 SCP5_5 SCP6_5 Register Description Selected Vertical Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected Vertical Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. Vertical Sequence Change Position No.1 for Field 5. Vertical Sequence Change Position No.2 for Field 5. Vertical Sequence Change Position No.3 for Field 5. Vertical Sequence Change Position No.4 for Field 5. VD Field Length (Number of Lines) for Field 5. HD Line Length (Number of Pixels) for Last Line in Field 5. Selected Second Vertical Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. MSB for 13-Bit Last Line Length VSG Active Line 1. VSG Active Line 2. (If No Second Line Is Needed, Set to Same as Line 1 or Maximum). Vertical Sequence Change Position No.5 for Field 5. Vertical Sequence Change Position No.6 for Field 5.
F9
FA FB FC FD
FE
FF
Rev. A | Page 86 of 96
AD9925 COMPLETE LISTING FOR REGISTER BANK 3
All vertical pattern group and vertical sequence registers are SCP updated. Default register values are undefined. Table 74. XV7 and XV8 Pattern Group 0 (VPAT0) Registers
Address 00 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_0 XV8POL_0 UNUSED XV78LEN_0 XV7TOG1_0 XV7TOG2_0 XV7TOG3_0 XV8TOG1_0 XV8TOG2_0 XV8TOG3_0 XV7TOG4_0 XV8TOG4_0 UNUSED UNUSED UNUSED Register Description VPAT0 XV7 Start Polarity VPAT0 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT0 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
01 02 03 04 05 06 07
Table 75. XV7 and XV8 Pattern Group 1 (VPAT1) Registers
Address 08 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_1 XV8POL_1 UNUSED XV78LEN_1 XV7TOG1_1 XV7TOG2_1 XV7TOG3_1 XV8TOG1_1 XV8TOG2_1 XV8TOG3_1 XV7TOG4_1 XV8TOG4_1 UNUSED UNUSED UNUSED Register Description VPAT1 XV7 Start Polarity VPAT1 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT2 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
09 0A 0B 0C 0D 0E 0F
Rev. A | Page 87 of 96
AD9925
Table 76. XV7 and XV8 Pattern Group 2 (VPAT2) Registers
Address 10 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_2 XV8POL_2 UNUSED XV78LEN_2 XV7TOG1_2 XV7TOG2_2 XV7TOG3_2 XV8TOG1_2 XV8TOG2_2 XV8TOG3_2 XV7TOG4_2 XV8TOG4_2 UNUSED UNUSED UNUSED Register Description VPAT2 XV7 Start Polarity VPAT2 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT2 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
11 12 13 14 15 16 17
Table 77. XV7 and XV8 Pattern Group 3 (VPAT3) Registers
Address 18 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_3 XV8POL_3 UNUSED XV78LEN_3 XV7TOG1_3 XV7TOG2_3 XV7TOG3_3 XV8TOG1_3 XV8TOG2_3 XV8TOG3_3 XV7TOG4_3 XV8TOG4_3 UNUSED UNUSED UNUSED Register Description VPAT3 XV7 Start Polarity VPAT3 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT3 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
19 1A 1B 1C 1D 1E 1F
Table 78. XV7 and XV8 Pattern Group 4 (VPAT4) Registers
Address 20 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_4 XV8POL_4 UNUSED XV78LEN_4 XV7TOG1_4 XV7TOG2_4 XV7TOG3_4 XV8TOG1_4 XV8TOG2_4 XV8TOG3_4 XV7TOG4_4 XV8TOG4_4 UNUSED UNUSED UNUSED Register Description VPAT4 XV7 Start Polarity VPAT4 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT4 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
21 22 23 24 25 26 27
Rev. A | Page 88 of 96
AD9925
Table 79. XV7 and XV8 Pattern Group 5 (VPAT5) Registers
Address 28 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_5 XV8POL_5 UNUSED XV78LEN_5 XV7TOG1_5 XV7TOG2_5 XV7TOG3_5 XV8TOG1_5 XV8TOG2_5 XV8TOG3_5 XV7TOG4_5 XV8TOG4_5 UNUSED UNUSED UNUSED Register Description VPAT5 XV7 Start Polarity VPAT5 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT5 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
29 2A 2B 2C 2D 2E 2F
Table 80. XV7 and XV8 Pattern Group 6 (VPAT6) Registers
Address 30 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_6 XV8POL_6 UNUSED XV78LEN_6 XV7TOG1_6 XV7TOG2_6 XV7TOG3_6 XV8TOG1_6 XV8TOG2_6 XV8TOG3_6 XV7TOG4_6 XV8TOG4_6 UNUSED UNUSED UNUSED Register Description VPAT6 XV7 Start Polarity VPAT6 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT6 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
31 32 33 34 35 36 37
Table 81. XV7 and XV8 Pattern Group 7 (VPAT7) Registers
Address 38 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_7 XV8POL_7 UNUSED XV78LEN_7 XV7TOG1_7 XV7TOG2_7 XV7TOG3_7 XV8TOG1_7 XV8TOG2_7 XV8TOG3_7 XV7TOG4_7 XV8TOG4_7 UNUSED UNUSED UNUSED Register Description VPAT7 XV7 Start Polarity VPAT7 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT7 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
39 3A 3B 3C 3D 3E 3F
Rev. A | Page 89 of 96
AD9925
Table 82. XV7 and XV8 Pattern Group 8 (VPAT8) Registers
Address 40 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_8 XV8POL_8 UNUSED XV78LEN_8 XV7TOG1_8 XV7TOG2_8 XV7TOG3_8 XV8TOG1_8 XV8TOG2_8 XV8TOG3_8 XV7TOG4_8 XV8TOG4_8 UNUSED UNUSED UNUSED Register Description VPAT8 XV7 Start Polarity VPAT8 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT8 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
41 42 43 44 45 46 47
Table 83. XV7 and XV8 Pattern Group 9 (VPAT9) Registers
Address 48 Data Bit Content [0] [1] [11:2] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [23:0] [23:0] [23:0] Default Value X X X X X X X X X X X X X X X Register Name XV7POL_9 XV8POL_9 UNUSED XV78LEN_9 XV7TOG1_9 XV7TOG2_9 XV7TOG3_9 XV8TOG1_9 XV8TOG2_9 XV8TOG3_9 XV7TOG4_9 XV8TOG4_9 UNUSED UNUSED UNUSED Register Description VPAT9 XV7 Start Polarity VPAT9 XV8 Start Polarity Unused Total Length of XV7 and XV8 Pattern for VPAT9 XV7 Toggle Position 1 XV7 Toggle Position 2 XV7 Toggle Position 3 XV8 Toggle Position 1 XV8 Toggle Position 2 XV8 Toggle Position 3 XV7 Toggle Position 4 XV8 Toggle Position 4 Unused Unused Unused
49 4A 4B 4C 4D 4E 4F
Table 84. XV7 and XV8 Vertical Sequence 0 Registers
Address 50 Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_0 UNUSED XV78START_0 XV78REPO_0 XV78REPE_0 XV78HOLDEN_0 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8,1: Enable Hold Area for XV7 and XV8 Unused Unused
51 52
53
Rev. A | Page 90 of 96
AD9925
Table 85. XV7 and XV8 Vertical Sequence 1 Registers
Address 54 Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_1 UNUSED XV78START_1 XV78REPO_1 XV78REPE_1 XV78HOLDEN_1 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
55 56 57
Table 86. XV7 and XV8 Vertical Sequence 2 Registers
Address 58 Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_2 UNUSED XV78START_2 XV78REPO_2 XV78REPE_2 XV78HOLDEN_2 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
59 5A 5B
Table 87. XV7 and XV8 Vertical Sequence 3 Registers
Address 5C Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_3 UNUSED XV78START_3 XV78REPO_3 XV78REPE_3 XV78HOLDEN_3 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
5D 5E 5F
Table 88. XV7 and XV8 Vertical Sequence 4 Registers
Address 60 Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_4 UNUSED XV78START_4 XV78REPO_4 XV78REPE_4 XV78HOLDEN_4 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
61 62 63
Rev. A | Page 91 of 96
AD9925
Table 89. XV7 and XV8 Vertical Sequence 5 Registers
Address 64 Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_5 UNUSED XV78START_5 XV78REPO_5 XV78REPE_5 XV78HOLDEN_5 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
65 66 67
Table 90. XV7 and XV8 Vertical Sequence 6 Registers
Address 68 Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_6 UNUSED XV78START_6 XV78REPO_6 XV78REPE_6 XV78HOLDEN_6 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
69 6A 6B
Table 91. XV7 and XV8 Vertical Sequence 7 Registers
Address 6C Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_7 UNUSED XV78START_7 XV78REPO_7 XV78REPE_7 XV78HOLDEN_7 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
6D 6E 6F
Table 92. XV7 and XV8 Vertical Sequence 8 Registers
Address 70 Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_8 UNUSED XV78START_8 XV78REPO_8 XV78REPE_8 XV78HOLDEN_8 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
71 72 73
Rev. A | Page 92 of 96
AD9925
Table 93. XV7 and XV8 Vertical Sequence 9 Registers
Address 74 Data Bit Content [0] [11:1] [23:12] [11:0] [23:12] [0] [23:1] [23:0] Default Value X X X X X X X X Register Name HOLD_9 UNUSED XV78START_9 XV78REPO_9 XV78REPE_9 XV78HOLDEN_9 UNUSED UNUSED Register Description 0: Vertical Masking Operation, 1: Hold Area instead of Vertical Masking Unused Start Position for XV7 and XV8 Number of Selected XV7, XV8 Repetitions for Odd Lines Number of Selected XV7, XV8 Repetitions for Even Lines 0: No Hold Area for XV7 and XV8, 1: Enable Hold Area for XV7 and XV8 Unused Unused
75 76 77
Rev. A | Page 93 of 96
AD9925 OUTLINE DIMENSIONS
8.00 BSC SQ A1 CORNER INDEX AREA
11 10 9 8 7 6 5 4 3 2 1 A
BALL A1 INDICATOR 6.50 BSC SQ BOTTOM VIEW
TOP VIEW
B C D E F G H J K L
0.65 BSC
0.75 REF
DETAIL A 1.40 MAX
DETAILA
0.40 0.25 0.45 0.40 0.35 SEATING PLANE
1.00 0.85
0.10 MAX COPLANARITY
BALL DIAMETER
Figure 78. 96-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-96) Dimensions shown in millimeters
ORDERING GUIDE
Models AD9925BBCZT1 AD9925BBCZRL1
P PT
Temperature Range -25C to +85C -25C to +85C
Package Description CSP_BGA CSP_BGA Tape and Reel
Option BC-96 BC-96
1
TP PT
Z = Pb-free part.
Rev. A | Page 94 of 96
AD9925 NOTES
Rev. A | Page 95 of 96
AD9925 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04637-0-10/04(A)
Rev. A | Page 96 of 96

▲Up To Search▲

Price & Availability of AD9925

	To Download AD9925 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .